Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > ADDRMAP5 (DDRC) Register

ADDRMAP5 (DDRC) Register

ADDRMAP5 (DDRC) Register Description

Register NameADDRMAP5
Relative Address0x0000000214
Absolute Address 0x00FD070214 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAddress Map Register 5

This register is static. Static registers can only be written when the controller is in reset.

ADDRMAP5 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addrmap_row_b1127:24rwNormal read/write0x0Selects the HIF address bit used as row address bit 11.
Valid Range: 0 to 11, and 15
Internal Base: 17
The selected HIF address bit is determined by adding the internal base to the value of this field.
If set to 15, row address bit 11 is set to 0.
addrmap_row_b2_1019:16rwNormal read/write0x0Selects the HIF address bits used as row address bits 2 to 10.
Valid Range: 0 to 11, and 15
Internal Base: 8 (for row address bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10)
The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. When value 15 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.
addrmap_row_b111:8rwNormal read/write0x0Selects the HIF address bits used as row address bit 1.
Valid Range: 0 to 11
Internal Base: 7
The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field.
addrmap_row_b0 3:0rwNormal read/write0x0Selects the HIF address bits used as row address bit 0.
Valid Range: 0 to 11
Internal Base: 6
The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field.