Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > ADDRMAP6 (DDRC) Register

ADDRMAP6 (DDRC) Register

ADDRMAP6 (DDRC) Register Description

Register NameADDRMAP6
Relative Address0x0000000218
Absolute Address 0x00FD070218 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAddress Map Register 6

This register is static. Static registers can only be written when the controller is in reset.

ADDRMAP6 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
lpddr3_6gb_12gb31rwNormal read/write0x0Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use.
- 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]==2'b11 is considered as invalid
- 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid
addrmap_row_b1527:24rwNormal read/write0x0Selects the HIF address bit used as row address bit 15.
Valid Range: 0 to 11, and 15
Internal Base: 21
The selected HIF address bit is determined by adding the internal base to the value of this field.
If set to 15, row address bit 15 is set to 0.
addrmap_row_b1419:16rwNormal read/write0x0Selects the HIF address bit used as row address bit 14.
Valid Range: 0 to 11, and 15
Internal Base: 20
The selected HIF address bit is determined by adding the internal base to the value of this field.
If set to 15, row address bit 14 is set to 0.
addrmap_row_b1311:8rwNormal read/write0x0Selects the HIF address bit used as row address bit 13.
Valid Range: 0 to 11, and 15
Internal Base: 19
The selected HIF address bit is determined by adding the internal base to the value of this field.
If set to 15, row address bit 13 is set to 0.
addrmap_row_b12 3:0rwNormal read/write0x0Selects the HIF address bit used as row address bit 12.
Valid Range: 0 to 11, and 15
Internal Base: 18
The selected HIF address bit is determined by adding the internal base to the value of this field.
If set to 15, row address bit 12 is set to 0.