Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > ADDRMAP7 (DDRC) Register

ADDRMAP7 (DDRC) Register

ADDRMAP7 (DDRC) Register Description

Register NameADDRMAP7
Relative Address0x000000021C
Absolute Address 0x00FD07021C (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAddress Map Register 7

This register is static. Static registers can only be written when the controller is in reset.

ADDRMAP7 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addrmap_row_b1711:8rwNormal read/write0x0Selects the HIF address bit used as row address bit 17.
Valid Range: 0 to 10, and 15
Internal Base: 23
The selected HIF address bit is determined by adding the internal base to the value of this field.
If set to 15, row address bit 17 is set to 0.
addrmap_row_b16 3:0rwNormal read/write0x0Selects the HIF address bit used as row address bit 16.
Valid Range: 0 to 11, and 15
Internal Base: 22
The selected HIF address bit is determined by adding the internal base to the value of this field.
If set to 15, row address bit 16 is set to 0.