Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > ADDRMAP8 (DDRC) Register

ADDRMAP8 (DDRC) Register

ADDRMAP8 (DDRC) Register Description

Register NameADDRMAP8
Relative Address0x0000000220
Absolute Address 0x00FD070220 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAddress Map Register 8

This register is static. Static registers can only be written when the controller is in reset.

ADDRMAP8 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
addrmap_bg_b112:8rwNormal read/write0x0Selects the HIF address bits used as bank group address bit 1.
Valid Range: 0 to 30, and 31
Internal Base: 3
The selected HIF address bit for each of the bank group address bits is determined by adding the internal base to the value of this field.
If set to 31, bank group address bit 1 is set to 0.
addrmap_bg_b0 4:0rwNormal read/write0x0Selects the HIF address bits used as bank group address bit 0.
Valid Range: 0 to 30
Internal Base: 2
The selected HIF address bit for each of the bank group address bits is determined by adding the internal base to the value of this field.