Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > DBGCAM (DDRC) Register

DBGCAM (DDRC) Register

DBGCAM (DDRC) Register Description

Register NameDBGCAM
Relative Address0x0000000308
Absolute Address 0x00FD070308 (DDRC)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionCAM Debug Register

This register is dynamic. Dynamic registers can be written at any time during operation.

DBGCAM (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
dbg_stall_rd31roRead-only0x0Stall for Read channel
FOR DEBUG ONLY
dbg_stall_wr30roRead-only0x0Stall for Write channel
FOR DEBUG ONLY
wr_data_pipeline_empty29roRead-only0x0This bit indicates that the write data pipeline on the DFI interface is empty.
This register is intended to be polled after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed.
rd_data_pipeline_empty28roRead-only0x0This bit indicates that the read data pipeline on the DFI interface is empty.
This register is intended to be polled after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed.
dbg_wr_q_empty26roRead-only0x0When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose.
An example use-case scenario: When Controller enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time.
FOR DEBUG ONLY
dbg_rd_q_empty25roRead-only0x0When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose.
An example use-case scenario: When Controller enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time.
FOR DEBUG ONLY
dbg_stall24roRead-only0x0Stall
FOR DEBUG ONLY
dbg_w_q_depth22:16roRead-only0x0Write queue depth
FOR DEBUG ONLY
dbg_lpr_q_depth14:8roRead-only0x0Low priority read queue depth
FOR DEBUG ONLY
dbg_hpr_q_depth 6:0roRead-only0x0High priority read queue depth
FOR DEBUG ONLY