DBGCAM (DDRC) Register Description
| Register Name | DBGCAM |
|---|---|
| Offset Address | 0x0000000308 |
| Absolute Address | 0x00FD070308 (DDRC) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | CAM Debug Register |
This register is dynamic. Dynamic registers can be written at any time during operation.
DBGCAM (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| dbg_stall_rd | 31 | roRead-only | 0x0 | Stall for Read channel FOR DEBUG ONLY |
| dbg_stall_wr | 30 | roRead-only | 0x0 | Stall for Write channel FOR DEBUG ONLY |
| wr_data_pipeline_empty | 29 | roRead-only | 0x0 | This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. |
| rd_data_pipeline_empty | 28 | roRead-only | 0x0 | This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. |
| dbg_wr_q_empty | 26 | roRead-only | 0x0 | When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. An example use-case scenario: When Controller enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time. FOR DEBUG ONLY |
| dbg_rd_q_empty | 25 | roRead-only | 0x0 | When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. An example use-case scenario: When Controller enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time. FOR DEBUG ONLY |
| dbg_stall | 24 | roRead-only | 0x0 | Stall FOR DEBUG ONLY |
| dbg_w_q_depth | 22:16 | roRead-only | 0x0 | Write queue depth FOR DEBUG ONLY |
| dbg_lpr_q_depth | 14:8 | roRead-only | 0x0 | Low priority read queue depth FOR DEBUG ONLY |
| dbg_hpr_q_depth | 6:0 | roRead-only | 0x0 | High priority read queue depth FOR DEBUG ONLY |