Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > PCFGQOS0_5 (DDRC) Register

PCFGQOS0_5 (DDRC) Register

PCFGQOS0_5 (DDRC) Register Description

Register NamePCFGQOS0_5
Relative Address0x0000000804
Absolute Address 0x00FD070804 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPort 5 Read QoS Configuration Register 0

This register is quasi-dynamic group 3. Group 3 registers can only be written when the controller is empty.

PCFGQOS0_5 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
rqos_map_region121:20rwNormal read/write0x0This bitfield indicates the traffic class of region 1.
Valid values are:
0: LPR, 1: VPR, 2: HPR.
For dual address queue configurations, region1 maps to the blue address queue.
In this case, valid values are
0: LPR and 1: VPR only.
rqos_map_region017:16rwNormal read/write0x0This bitfield indicates the traffic class of region 0.
Valid values are:
0: LPR, 1: VPR, 2: HPR.
For dual address queue configurations, region 0 maps to the blue address queue.
In this case, valid values are:
0: LPR and 1: VPR only.
rqos_map_level1 3:0rwNormal read/write0x0Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos.
Note that for PA, arqos values are used directly as port priorities, where the higher the value corresponds to higher port priority.
All of the map_level* registers must be set to distinct values.