Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > PCFGQOS1_5 (DDRC) Register

PCFGQOS1_5 (DDRC) Register

PCFGQOS1_5 (DDRC) Register Description

Register NamePCFGQOS1_5
Relative Address0x0000000808
Absolute Address 0x00FD070808 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPort 5 Read QoS Configuration Register 1

This register is quasi-dynamic group 3. Group 3 registers can only be written when the controller is empty.

PCFGQOS1_5 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
rqos_map_timeoutr26:16rwNormal read/write0x0Specifies the timeout value for transactions mapped to the red address queue.
rqos_map_timeoutb10:0rwNormal read/write0x0Specifies the timeout value for transactions mapped to the blue address queue.