Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > PCFGW_5 (DDRC) Register

PCFGW_5 (DDRC) Register

PCFGW_5 (DDRC) Register Description

Register NamePCFGW_5
Relative Address0x0000000778
Absolute Address 0x00FD070778 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00004000
DescriptionPort 5 Configuration Write Register

This register is static. Static registers can only be written when the controller is in reset.

PCFGW_5 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
wr_port_pagematch_en14rwNormal read/write0x1If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit register.
wr_port_urgent_en13rwNormal read/write0x0If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register.
Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command).
wr_port_aging_en12rwNormal read/write0x0If set to 1, enables aging function for the write channel of the port.
wr_port_priority 9:0rwNormal read/write0x0Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5 bits of the write aging counter must be set to 0. When the aging counter becomes 0, the corresponding port channel will have the highest priority level.
Note: The two LSBs of this register field are tied internally to 2'b00.