Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > PCFGWQOS0_4 (DDRC) Register

PCFGWQOS0_4 (DDRC) Register

PCFGWQOS0_4 (DDRC) Register Description

Register NamePCFGWQOS0_4
Relative Address0x000000075C
Absolute Address 0x00FD07075C (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPort 4 Write QoS Configuration Register 0

This register is quasi-dynamic group 3. Group 3 registers can only be written when the controller is empty.

PCFGWQOS0_4 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
wqos_map_region121:20rwNormal read/write0x0This bitfield indicates the traffic class of region 1.
Valid values are:
0: NPW, 1: VPW.
wqos_map_region017:16rwNormal read/write0x0This bitfield indicates the traffic class of region 0.
Valid values are:
0: NPW, 1: VPW.
wqos_map_level 3:0rwNormal read/write0x0Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which corresponds to awqos.
Note that for PA, awqos values are used directly as port priorities, where the higher the value corresponds to higher port priority.