Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > PCFGWQOS1_3 (DDRC) Register

PCFGWQOS1_3 (DDRC) Register

PCFGWQOS1_3 (DDRC) Register Description

Register NamePCFGWQOS1_3
Relative Address0x00000006B0
Absolute Address 0x00FD0706B0 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPort 3 Write QoS Configuration Register 1

This register is quasi-dynamic group 3. Group 3 registers can only be written when the controller is empty.

PCFGWQOS1_3 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
wqos_map_timeout10:0rwNormal read/write0x0Specifies the timeout value for write transactions.