Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > PERFHPR1 (DDRC) Register

PERFHPR1 (DDRC) Register

PERFHPR1 (DDRC) Register Description

Register NamePERFHPR1
Relative Address0x000000025C
Absolute Address 0x00FD07025C (DDRC)
Width32
TyperwNormal read/write
Reset Value0x0F000001
DescriptionHigh Priority Read CAM Register 1

This register is quasi-dynamic group 3. Group 3 registers can only be written when the controller is empty.

PERFHPR1 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
hpr_xact_run_length31:24rwNormal read/write0xFNumber of transactions that are serviced once the HPR queue goes critical is the smaller of:
- (a) This number
- (b) Number of transactions available.
Unit: Transaction.
FOR PERFORMANCE ONLY.
hpr_max_starve15:0rwNormal read/write0x1Number of clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies.
Unit: Clock cycles.
FOR PERFORMANCE ONLY.