Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > PERFLPR1 (DDRC) Register

PERFLPR1 (DDRC) Register

PERFLPR1 (DDRC) Register Description

Register NamePERFLPR1
Relative Address0x0000000264
Absolute Address 0x00FD070264 (DDRC)
TyperwNormal read/write
Reset Value0x0F00007F
DescriptionLow Priority Read CAM Register 1

This register is quasi-dynamic group 3. Group 3 registers can only be written when the controller is empty.

PERFLPR1 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
lpr_xact_run_length31:24rwNormal read/write0xFNumber of transactions that are serviced once the LPR queue goes critical is the smaller of:
- (a) This number
- (b) Number of transactions available.
Unit: Transaction.
lpr_max_starve15:0rwNormal read/write0x7FNumber of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies.
Unit: Clock cycles.