Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > PERFVPR1 (DDRC) Register
|Absolute Address||0x00FD070274 (DDRC)|
|Description||Variable Priority Read CAM Register 1|
This register is static. Static registers can only be written when the controller is in reset.
|Field Name||Bits||Type||Reset Value||Description|
|vpr_timeout_range||10:0||rwNormal read/write||0x0||Indicates the range of the timeout value that is used for grouping the expired VPR commands in the CAM in DDRC. For example, if the register value is set to 0xF, then the priorities of all the VPR commands whose timeout counters are 15 or below will be considered as expired-VPR commands when the timeout value of any of the VPR commands reach 0. The expired-VPR commands, when present, are given higher priority than HPR commands. The VPR commands are expected to consist of largely page hit traffic and by grouping them together the bus utilization is expected to increase. This register applies to transactions inside the DDRC only.|
The Max value for this register is 0x7FF and the Min value is 0x0.
When programmed to the Max value of 0x7FF, all the VPR commands that come in to DDRC will time-out right-away and will be considered as expired-VPR.
When programmed to the Min value of 0x0, the timer of each command would have to reach a value of 0 before it will be considered as expired-VPR.
Unit: Clock cycles.
FOR PERFORMANCE ONLY.