Zynq UltraScale+ Devices Register Reference > Module Summary > DDRC Module > SCHED (DDRC) Register

SCHED (DDRC) Register

SCHED (DDRC) Register Description

Register NameSCHED
Relative Address0x0000000250
Absolute Address 0x00FD070250 (DDRC)
Width32
TyperwNormal read/write
Reset Value0x00002005
DescriptionScheduler Control Register

All register fields are static, unless described otherwise in the register field description. Static registers can only be written when the controller is in reset.

SCHED (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
rdwr_idle_gap30:24rwNormal read/write0x0When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty.
The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternative store.
When prefer write over read is set this is reversed.
0x0 is a legal value for this register. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true.
FOR PERFORMANCE ONLY
go2critical_hysteresis23:16rwNormal read/write0x0UNUSED
lpr_num_entries13:8rwNormal read/write0x20Number of entries in the low priority transaction store is this value + 1.
(64 - (SCHED.lpr_num_entries + 1)) is the number of entries available for the high priority transaction store.
Setting this to maximum value allocates all entries to low priority transaction store.
Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high priority transaction store.
Note: In ECC configurations, the numbers of write and low priority read credits issued is one less than in the non-ECC case.
One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests arising out of single bit error correction RMW operation.
pageclose 2rwNormal read/write0x1If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge.
If false, the bank remains open until there is a need to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy.
The pageclose feature provides a midway between Open and Close page policies.
FOR PERFORMANCE ONLY.
Programming Mode: Quasi-dynamic Group 3
prefer_write 1rwNormal read/write0x0If set then the bank selector prefers writes over reads.
FOR DEBUG ONLY.
force_low_pri_n 0rwNormal read/write0x1Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Priority Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write side, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off Bypass path for read commands.
FOR PERFORMANCE ONLY.