Zynq UltraScale+ Devices Register Reference > Module Summary > FPD_GPV Module > afifm2M_intfpd_ar_p (FPD_GPV) Register

afifm2M_intfpd_ar_p (FPD_GPV) Register

afifm2M_intfpd_ar_p (FPD_GPV) Register Description

Register Nameafifm2M_intfpd_ar_p
Relative Address0x0000047124
Absolute Address 0x00FD747124 (FPD_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAR channel peak rate

afifm2M_intfpd_ar_p (FPD_GPV) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ar_p31:24rwNormal read/write0x0channel peak rate. 8-bit fraction of the number of transfers per cycle. A value of 0x80 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x40 sets a rate of one transaction every 4 cycles, etc.