Zynq UltraScale+ Devices Register Reference > Module Summary > FPD_GPV Module > afifm2M_intfpd_ar_r (FPD_GPV) Register

afifm2M_intfpd_ar_r (FPD_GPV) Register

afifm2M_intfpd_ar_r (FPD_GPV) Register Description

Register Nameafifm2M_intfpd_ar_r
Relative Address0x000004712C
Absolute Address 0x00FD74712C (FPD_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAR channel average rate

afifm2M_intfpd_ar_r (FPD_GPV) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ar_r31:20rwNormal read/write0x0channel average rate. 12-bit fraction of the number of transfers per cycle. A value of 0x800 (decimal 0.5) sets a rate of one transaction every 2 cycles. A value of 0x400 sets a rate of one transaction every 4 cycles, etc.