Zynq UltraScale+ Devices Register Reference > Module Summary > FPD_GPV Module > afifm2M_intfpd_max_comb_ot (FPD_GPV) Register

afifm2M_intfpd_max_comb_ot (FPD_GPV) Register

afifm2M_intfpd_max_comb_ot (FPD_GPV) Register Description

Register Nameafifm2M_intfpd_max_comb_ot
Relative Address0x0000047114
Absolute Address 0x00FD747114 (FPD_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMaximum number of combined outstanding transactions

A value of 0 for both the integer and fractional parts disables the programmable regulation so that the configuration limits apply. A value of 0 for the fractional part programs disables the regulation of fractional outstanding transactions. The regulation of the combined outstanding transaction limit also requires that you set the en_awar_ot control bit of the QoS control register.

afifm2M_intfpd_max_comb_ot (FPD_GPV) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
awar_max_oti14:8rwNormal read/write0x0Integer part of max combined outstanding AW/AR addresses.
awar_max_otf 7:0rwNormal read/write0x0Fraction part of max combined outstanding AW/AR addresses.

The maximum combined outstanding transactions register enables you to program the maximum number of address requests for the AR and AW channels. The combined limit is applied after any individual channel limits.