Zynq UltraScale+ Devices Register Reference > Module Summary > FPD_GPV Module > afifm2M_intfpd_max_ot (FPD_GPV) Register

afifm2M_intfpd_max_ot (FPD_GPV) Register

afifm2M_intfpd_max_ot (FPD_GPV) Register Description

Register Nameafifm2M_intfpd_max_ot
Relative Address0x0000047110
Absolute Address 0x00FD747110 (FPD_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMaximum number of outstanding transactions

A value of 0 for both the integer and fractional parts disables the programmable regulation so that the NIC-301 base product configuration limits apply. A value of 0 for the fractional part programs disables the regulation of fractional outstanding transactions. The AW and AR outstanding transaction limits are enabled when you set the corresponding en_aw_ot or en_ar_ot control bits of the QoS control register.

afifm2M_intfpd_max_ot (FPD_GPV) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ar_max_oti29:24rwNormal read/write0x0Integer part of max outstanding AR addresses.
ar_max_otf23:16rwNormal read/write0x0Fraction part of max outstanding AR addresses.
aw_max_oti13:8rwNormal read/write0x0Integer part of max outstanding AW addresses.
aw_max_otf 7:0rwNormal read/write0x0Fraction part of max outstanding AW addresses.

The maximum number of outstanding transactions register enables you to program the maximum number of address requests for the AR and AW channels. The outstanding transaction limits have an integer part and a fractional part.