Zynq UltraScale+ Devices Register Reference > Module Summary > FPD_GPV Module > afifm2M_intfpd_qos_cntl (FPD_GPV) Register

afifm2M_intfpd_qos_cntl (FPD_GPV) Register

afifm2M_intfpd_qos_cntl (FPD_GPV) Register Description

Register Nameafifm2M_intfpd_qos_cntl
Relative Address0x000004710C
Absolute Address 0x00FD74710C (FPD_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionThe QoS control register contains the enable bits for all the regulators.

By default, all of the bits are set to 0, and no regulation is enabled. Regulation only takes place when both the enable bit is set, and its corresponding regulation value is non-zero. The QoS regulators are reset whenever they are re-enabled.

afifm2M_intfpd_qos_cntl (FPD_GPV) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
en_awar_ot 7rwNormal read/write0x0Enable combined regulation of outstanding transactions.
en_ar_ot 6rwNormal read/write0x0Enable regulation of outstanding read transactions.
en_aw_ot 5rwNormal read/write0x0Enable regulation of outstanding write transactions.
en_awar_rate 2rwNormal read/write0x0Enable combined AW/AR rate regulation.
en_ar_rate 1rwNormal read/write0x0Enable AR rate regulation.
en_aw_rate 0rwNormal read/write0x0Enable AW rate regulation.