Register Name | Offset Address | Width | Type | Reset Value | Description |
ERR_CTRL | 0x0000000000 | 32 | rwNormal read/write | 0x00000000 | Control register |
ISR | 0x0000000010 | 32 | wtcReadable, write a 1 to clear | 0x00000000 | Interrupt Status Register |
IMR | 0x0000000014 | 32 | roRead-only | 0x00000001 | Interrupt Mask Register |
IEN | 0x0000000018 | 32 | woWrite-only | 0x00000000 | Interrupt Enable Register |
IDS | 0x000000001C | 32 | woWrite-only | 0x00000000 | Interrupt Disable Register |
CONFIG_0 | 0x0000000020 | 32 | rwNormal read/write | 0x00000F0F | CPU Core Configuration |
CONFIG_1 | 0x0000000024 | 32 | rwNormal read/write | 0x00000000 | L2 Configuration |
RVBARADDR0L | 0x0000000040 | 32 | rwNormal read/write | 0xFFFF0000 | Reset Vector Base Address |
RVBARADDR0H | 0x0000000044 | 32 | rwNormal read/write | 0x00000000 | Reset Vector Base Address |
RVBARADDR1L | 0x0000000048 | 32 | rwNormal read/write | 0xFFFF0000 | Reset Vector Base Address |
RVBARADDR1H | 0x000000004C | 32 | rwNormal read/write | 0x00000000 | Reset Vector Base Address |
RVBARADDR2L | 0x0000000050 | 32 | rwNormal read/write | 0xFFFF0000 | Reset Vector Base Address |
RVBARADDR2H | 0x0000000054 | 32 | rwNormal read/write | 0x00000000 | Reset Vector Base Address |
RVBARADDR3L | 0x0000000058 | 32 | rwNormal read/write | 0xFFFF0000 | Reset Vector Base Address |
RVBARADDR3H | 0x000000005C | 32 | rwNormal read/write | 0x00000000 | Reset Vector Base Address |
ACE_CTRL | 0x0000000060 | 32 | rwNormal read/write | 0x000F000F | ACE Control Register |
SNOOP_CTRL | 0x0000000080 | 32 | rwNormal read/write | 0x00000000 | Snoop Control Register |
PWRCTL | 0x0000000090 | 32 | rwNormal read/write | 0x00000000 | Power Control Register |
PWRSTAT | 0x0000000094 | 32 | roRead-only | 0x00000000 | Power Status Register |