Zynq UltraScale+ Devices Register Reference > Module Summary > DP Module

DP Module

DP Module Description

Module NameDP Module
Modules of this TypeDP
Base Address0xFD4A0000 (DP)
DescriptionDisplayPort Controller

DP Module Register Summary

Register NameAddressWidthTypeReset ValueDescription
DP_LINK_BW_SET0x0000000032mixed0x00000000Sets the value of the main link bandwidth for the sink device.
DP_LANE_COUNT_SET0x0000000432mixed0x00000000To set the lane count
DP_ENHANCED_FRAME_EN0x0000000832mixed0x00000000To enable enhanced framing
DP_TRAINING_PATTERN_SET0x0000000C32mixed0x00000000To force training pattern
DP_LINK_QUAL_PATTERN_SET0x0000001032mixed0x00000000To transmit the link quality pattern
DP_SCRAMBLING_DISABLE0x0000001432mixed0x00000000DP_SCRAMBLING_DISABLE
DP_DOWNSPREAD_CTRL0x0000001832mixed0x00000000For down-spreading control
DP_SOFTWARE_RESET0x0000001C32mixed0x00000000Soft reset of DP Core
DP_COMP_PATTERN_80BIT_10x0000002032rw0x0000000032 bits of 80-bit custom pattern that is used for LINK quality test. These bits are valid when Bit 2 of DP_LINK_QUAL_PATTERN_SET 0x10 register is set to '1
DP_COMP_PATTERN_80BIT_20x0000002432rw0x00000000Description same as DP_COMP_PATTERN_80BIT_1 (0x20)
DP_COMP_PATTERN_80BIT_30x0000002832mixed0x00000000Description same as DP_COMP_PATTERN_80BIT_1 (0x20)
DP_TRANSMITTER_ENABLE0x0000008032mixed0x00000000Enable the basic operations of the transmitter.
DP_MAIN_STREAM_ENABLE0x0000008432mixed0x00000000Enable the transmission of main link video information.
DP_FORCE_SCRAMBLER_RESET0x000000C032mixed0x00000000Reads from this register always return 0x0.
DP_VERSION_REGISTER0x000000F832ro0x04010000Core version register
DP_CORE_ID0x000000FC32ro0x01020000Returns the unique identification code of the core and the current revision level
DP_AUX_COMMAND_REGISTER0x0000010032mixed0x00000000DP_AUX_COMMAND_REGISTER
DP_AUX_WRITE_FIFO0x0000010432mixed0x00000000. FIFO containing up to 16 bytes of write data for the current AUX channel command
DP_AUX_ADDRESS0x0000010832mixed0x00000000Specifies the address for the current AUX channel command.
DP_AUX_CLOCK_DIVIDER0x0000010C32mixed0x00000000. Contains the clock divider value for generating the internal 1MHz clock from the APB host interface clock. The clock divider register provides integer division only and does not support fractional APB clock rates (for example, set to 75 for a 75 MHz APB clock).
DP_TX_USER_FIFO_OVERFLOW0x0000011032mixed0x00000000. Indicates an overflow in the user FIFO. The event may occur if the video rate does not match the TU size programming.
DP_INTERRUPT_SIGNAL_STATE0x0000013032mixed0x00000000Contains the raw signal values for those conditions which may cause an interrupt.
DP_AUX_REPLY_DATA0x0000013432mixed0x00000000Maps to the internal FIFO which contains up to 16 bytes of information received during the AUX channel reply. Reply data is read from the FIFO starting with byte 0. The number of bytes in the FIFO corresponds to the number of bytes requested.
DP_AUX_REPLY_CODE0x0000013832mixed0x00000000Reply code received from the most recent AUX Channel request. The AUX Reply Code corresponds to the code from the DisplayPort specification
DP_AUX_REPLY_COUNT0x0000013C32mixed0x00000000Provides an internal counter of the number of AUX reply transactions received on the AUX Channel. Writing to this register clears the count.
DP_REPLY_DATA_COUNT0x0000014832mixed0x00000000Returns the total number of data bytes actually received during a transaction. This register does not use the length byte of the transaction header.
DP_REPLY_STATUS0x0000014C32mixed0x00000010DP_REPLY_STATUS
DP_HPD_DURATION0x0000015032mixed0x00000000DP_HPD_DURATION
DP_MAIN_STREAM_HTOTAL0x0000018032mixed0x00000000Specifies the total number of clocks in the horizontal framing period for the main stream video signal.
DP_MAIN_STREAM_VTOTAL0x0000018432mixed0x00000000Provides the total number of lines in the main stream video frame
DP_MAIN_STREAM_POLARITY0x0000018832mixed0x00000000Provides the polarity values for the video sync signals
DP_MAIN_STREAM_HSWIDTH0x0000018C32mixed0x00000000Sets the width of the horizontal sync pulse.
DP_MAIN_STREAM_VSWIDTH0x0000019032mixed0x00000000Sets the width of the vertical sync pulse.
DP_MAIN_STREAM_HRES0x0000019432mixed0x00000000Horizontal resolution of the main stream video source
DP_MAIN_STREAM_VRES0x0000019832mixed0x00000000Vertical resolution of the main stream video source
DP_MAIN_STREAM_HSTART0x0000019C32mixed0x00000000Number of clocks between the leading edge of the horizontal sync and the start of active data
DP_MAIN_STREAM_VSTART0x000001A032mixed0x00000000Number of lines between the leading edge of the vertical sync and the first line of active data.
DP_MAIN_STREAM_MISC00x000001A432mixed0x00000000Miscellaneous stream attributes.Implements the attribute information contained in the DisplayPort MISC0 register described in section 2.2.4 of the standard.
DP_MAIN_STREAM_MISC10x000001A832mixed0x00000000MAIN_STREAM_MISC1. Miscellaneous stream attributes.Implements the attribute information contained in the DisplayPort MISC1 register described in section 2.2.4 of the standard.
DP_MAIN_STREAM_M_VID0x000001AC32mixed0x00000000M value for the video stream as computed by the source core. If synchronous clocking mode is used, this register must be written with the M value.
DP_MSA_TRANSFER_UNIT_SIZE0x000001B032mixed0x00000040Sets the size of a transfer unit in the framing logic On reset, transfer size is set to 64.
DP_MAIN_STREAM_N_VID0x000001B432mixed0x00000000N value for the video stream as computed by the source core. If synchronous clocking mode is used, this register must be written with the N value.
DP_USER_PIX_WIDTH0x000001B832mixed0x00000001User pixel width size
DP_USER_DATA_COUNT_PER_LANE0x000001BC32mixed0x00000000This register is used to translate the number of pixels per line to the native internal 16-bit datapath.
DP_MIN_BYTES_PER_TU0x000001C432mixed0x00000000Programs source to use MIN number of bytes per transfer unit. The calculation should be done based on the DisplayPort specification.
DP_FRAC_BYTES_PER_TU0x000001C832mixed0x00000000Calculating MIN bytes per TU will often not be a whole number.This register is used to hold the fractional component
DP_INIT_WAIT0x000001CC32mixed0x00000020This register defines the number of initial wait cycles at the start of a new line by the Framing logic. This allows enough data to be buffered in the input FIFO.
DP_PHY_RESET0x0000020032mixed0x00010003Reset the transmitter PHY.
DP_TRANSMIT_PRBS70x0000023032mixed0x00000000Enable the pseudo random bit sequence 7 pattern transmission for link quality assessment. PRBS is generated by the DP transmit controller only. PRBS feature of Cadence GT is unused
DP_PHY_CLOCK_SELECT0x0000023432mixed0x00000000Instructs the PHY PLL to generate the proper clock frequency for the required link rate
DP_TX_PHY_POWER_DOWN0x0000023832mixed0x00000000Control PHY Power down
DP_PHY_PRECURSOR_LANE_00x0000024C32mixed0x00000000Set the pre-cursor level(post cursor 1for cadence GT) for lane 0 of the DisplayPort link
DP_PHY_PRECURSOR_LANE_10x0000025032mixed0x00000000Set the pre-cursor level(post cursor 1 for Cadence GT) for lane 1 of the DisplayPort link
DP_PHY_STATUS0x0000028032mixed0x00000000Provides the current status from the PHY.
DP_TX_AUDIO_CONTROL0x0000030032mixed0x00000000Enables audio stream packets in main link and provides buffer control.
DP_TX_AUDIO_CHANNELS0x0000030432rw0x00000000TX_AUDIO_CHANNELS. Used to input active channel count. Transmitter collects audio samples based on this information.
DP_TX_AUDIO_INFO_DATA00x0000030832wo0x00000000Word formatted as per CEA 861-C Info Frame.
DP_TX_AUDIO_INFO_DATA10x0000030C32wo0x00000000Word formatted as per CEA 861-C Info Frame.
DP_TX_AUDIO_INFO_DATA20x0000031032wo0x00000000Word formatted as per CEA 861-C Info Frame.
DP_TX_AUDIO_INFO_DATA30x0000031432wo0x00000000Word formatted as per CEA 861-C Info Frame.
DP_TX_AUDIO_INFO_DATA40x0000031832wo0x00000000Word formatted as per CEA 861-C Info Frame.
DP_TX_AUDIO_INFO_DATA50x0000031C32wo0x00000000Word formatted as per CEA 861-C Info Frame.
DP_TX_AUDIO_INFO_DATA60x0000032032wo0x00000000Word formatted as per CEA 861-C Info Frame.
DP_TX_AUDIO_INFO_DATA70x0000032432wo0x00000000Word formatted as per CEA 861-C Info Frame.
DP_TX_M_AUD0x0000032832mixed0x00000000M value of audio stream as computed by transmitter
DP_TX_N_AUD0x0000032C32mixed0x00000000TX_AUDIO_NAUD. N value of audio stream as computed by transmitter.
DP_TX_AUDIO_EXT_DATA00x0000033032wo0x00000000Word formatted as per Extension packet described in protocol specification. Extended packet is fixed to 32 Bytes length. The controller has buffer space for only one extended packet.
DP_TX_AUDIO_EXT_DATA10x0000033432wo0x000000002nd word of the 9 words of the extended packet
DP_TX_AUDIO_EXT_DATA20x0000033832wo0x000000003rd word of the 9 words of the extended packet
DP_TX_AUDIO_EXT_DATA30x0000033C32wo0x000000004th word of the 9 words of the extended packet
DP_TX_AUDIO_EXT_DATA40x0000034032wo0x000000005th word of the 9 words of the extended packet
DP_TX_AUDIO_EXT_DATA50x0000034432wo0x000000006th word of the 9 words of the extended packet
DP_TX_AUDIO_EXT_DATA60x0000034832wo0x000000007th word of the 9 words of the extended packet
DP_TX_AUDIO_EXT_DATA70x0000034C32wo0x000000008th word of the 9 words of the extended packet
DP_TX_AUDIO_EXT_DATA80x0000035032wo0x000000009th word of the 9 words of the extended packet
DP_INT_STATUS0x000003A032mixed0x00000000Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1.
DP_INT_MASK0x000003A432mixed0xFFFFF03FInterrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER.
DP_INT_EN0x000003A832mixed0x00000000Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0)
DP_INT_DS0x000003AC32mixed0x00000000Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1)
V_BLEND_BG_CLR_00x0000A00032mixed0x00000000V_BLEND_BG_CLR_0: Sets background color of the layers
V_BLEND_BG_CLR_10x0000A00432mixed0x00000000V_BLEND_BG_CLR_1: Sets background color of the layers
V_BLEND_BG_CLR_20x0000A00832mixed0x00000000V_BLEND_BG_CLR_2: Sets background color of the layers.
V_BLEND_SET_GLOBAL_ALPHA_REG0x0000A00C32mixed0x00000000To set the global alpha
V_BLEND_OUTPUT_VID_FORMAT0x0000A01432mixed0x00000000V_BLEND_OUTPUT_VID_FORMAT:
V_BLEND_LAYER0_CONTROL0x0000A01832mixed0x00000000V_BLEND_LAYER0_CONTROL: Layer 0 is always video pixel
V_BLEND_LAYER1_CONTROL0x0000A01C32mixed0x00000000V_BLEND_LAYER1_CONTROL: Layer 1 is always Graphcis
V_BLEND_RGB2YCBCR_COEFF00x0000A02032mixed0x00001000V_BLEND_RGB2YCBCR_COEFF0:Coefficient values from Matrix for output color space convertor. A total of 9 values are needed to form 3x3 matrix. The value is scaled by 2^12 and stored in 15-bit signed format.(1bit reserved). 12Bits out of the 15 represent fractional value and 2 bits for decimal value and one signed bit. The order of programming values is from v0 - v8
V_BLEND_RGB2YCBCR_COEFF10x0000A02432mixed0x00000000V_BLEND_RGB2YCBCR_COEFF1:Description same as V_BLEND_RGB2YCBCR_COEFF0
V_BLEND_RGB2YCBCR_COEFF20x0000A02832mixed0x00000000V_BLEND_RGB2YCBCR_COEFF2:Description same as V_BLEND_RGB2YCBCR_COEFF0
V_BLEND_RGB2YCBCR_COEFF30x0000A02C32mixed0x00000000V_BLEND_RGB2YCBCR_COEFF3:Description same as V_BLEND_RGB2YCBCR_COEFF0
V_BLEND_RGB2YCBCR_COEFF40x0000A03032mixed0x00001000V_BLEND_RGB2YCBCR_COEFF4:Description same as V_BLEND_RGB2YCBCR_COEFF0
V_BLEND_RGB2YCBCR_COEFF50x0000A03432mixed0x00000000V_BLEND_RGB2YCBCR_COEFF5:Description same as V_BLEND_RGB2YCBCR_COEFF0
V_BLEND_RGB2YCBCR_COEFF60x0000A03832mixed0x00000000V_BLEND_RGB2YCBCR_COEFF6:Description same as V_BLEND_RGB2YCBCR_COEFF0
V_BLEND_RGB2YCBCR_COEFF70x0000A03C32mixed0x00000000V_BLEND_RGB2YCBCR_COEFF7:Description same as V_BLEND_RGB2YCBCR_COEFF0
V_BLEND_RGB2YCBCR_COEFF80x0000A04032mixed0x00001000V_BLEND_RGB2YCBCR_COEFF8:Description same as V_BLEND_RGB2YCBCR_COEFF0
V_BLEND_IN1CSC_COEFF00x0000A04432mixed0x00001000V_BLEND_IN1CSC_COEFF0:Coefficient values from Matrix for input color space convertor(video). A total of 9 values are needed to form 3x3 matrix. The value is scaled by 2^12 and stored in 15-bit signed format.(1bit reserved). 12Bits out of the 15 represent fractional value and 2 bits for decimal value and one signed bit. The order of programming values is from v0 - v8
V_BLEND_IN1CSC_COEFF10x0000A04832mixed0x00000000V_BLEND_IN1CSC_COEFF1:Description same as V_BLEND_IN1CSC_COEFF0
V_BLEND_IN1CSC_COEFF20x0000A04C32mixed0x00000000V_BLEND_IN1CSC_COEFF2:Description same as V_BLEND_IN1CSC_COEFF0
V_BLEND_IN1CSC_COEFF30x0000A05032mixed0x00000000V_BLEND_IN1CSC_COEFF3:Description same as V_BLEND_IN1CSC_COEFF0
V_BLEND_IN1CSC_COEFF40x0000A05432mixed0x00001000V_BLEND_IN1CSC_COEFF4:Description same as V_BLEND_IN1CSC_COEFF0
V_BLEND_IN1CSC_COEFF50x0000A05832mixed0x00000000V_BLEND_IN1CSC_COEFF5:Description same as V_BLEND_IN1CSC_COEFF0
V_BLEND_IN1CSC_COEFF60x0000A05C32mixed0x00000000V_BLEND_IN1CSC_COEFF6:Description same as V_BLEND_IN1CSC_COEFF0
V_BLEND_IN1CSC_COEFF70x0000A06032mixed0x00000000V_BLEND_IN1CSC_COEFF7:CDescription same as V_BLEND_IN1CSC_COEFF0
V_BLEND_IN1CSC_COEFF80x0000A06432mixed0x00001000V_BLEND_IN1CSC_COEFF8:Description same as V_BLEND_IN1CSC_COEFF0
V_BLEND_LUMA_IN1CSC_OFFSET0x0000A06832mixed0x00000000V_BLEND_LUMA_IN1CSC_OFFSET: Offset values for Y before and after matrix multiplication for input color space conversion
V_BLEND_CR_IN1CSC_OFFSET0x0000A06C32mixed0x00000000V_BLEND_CR_IN1CSC_OFFSET: Offset values for CR before and after matrix multiplication for input color space conversion
V_BLEND_CB_IN1CSC_OFFSET0x0000A07032mixed0x00000000V_BLEND_CB_IN1CSC_OFFSET: Offset values for CB before and after matrix multiplication for input color space conversion
V_BLEND_LUMA_OUTCSC_OFFSET0x0000A07432mixed0x00000000V_BLEND_LUMA_OUTCSC_OFFSET: Offset values for Y before and after matrix multiplication for output color space conversion
V_BLEND_CR_OUTCSC_OFFSET0x0000A07832mixed0x00000000V_BLEND_CR_OUTCSC_OFFSET: Offset values for CR before and after matrix multiplication for output color space conversion
V_BLEND_CB_OUTCSC_OFFSET0x0000A07C32mixed0x00000000V_BLEND_CB_OUTCSC_OFFSET: Offset values for color CB before and after matrix multiplication for output color space conversion
V_BLEND_IN2CSC_COEFF00x0000A08032mixed0x00001000V_BLEND_IN2CSC_COEFF0:Coefficient values from Matrix for input color space convertor(graphics). A total of 9 values are needed to form 3x3 matrix. The value is scaled by 2^12 and stored in 15-bit signed format.(1bit reserved). 12Bits out of the 15 represent fractional value and 2 bits for decimal value and one signed bit. The order of programming values is from v0 - v8
V_BLEND_IN2CSC_COEFF10x0000A08432mixed0x00000000V_BLEND_IN2CSC_COEFF1:Description same as V_BLEND_IN2CSC_COEFF0
V_BLEND_IN2CSC_COEFF20x0000A08832mixed0x00000000V_BLEND_IN2CSC_COEFF2:Description same as V_BLEND_IN2CSC_COEFF0
V_BLEND_IN2CSC_COEFF30x0000A08C32mixed0x00000000V_BLEND_IN2CSC_COEFF3:Description same as V_BLEND_IN2CSC_COEFF0
V_BLEND_IN2CSC_COEFF40x0000A09032mixed0x00001000V_BLEND_IN2CSC_COEFF4:Description same as V_BLEND_IN2CSC_COEFF0
V_BLEND_IN2CSC_COEFF50x0000A09432mixed0x00000000V_BLEND_IN2CSC_COEFF5:Description same as V_BLEND_IN2CSC_COEFF0
V_BLEND_IN2CSC_COEFF60x0000A09832mixed0x00000000V_BLEND_IN2CSC_COEFF6:Description same as V_BLEND_IN2CSC_COEFF0
V_BLEND_IN2CSC_COEFF70x0000A09C32mixed0x00000000V_BLEND_IN2CSC_COEFF7:Description same as V_BLEND_IN2CSC_COEFF0
V_BLEND_IN2CSC_COEFF80x0000A0A032mixed0x00001000V_BLEND_IN2CSC_COEFF8:Description same as V_BLEND_IN2CSC_COEFF0
V_BLEND_LUMA_IN2CSC_OFFSET0x0000A0A432mixed0x00000000V_BLEND_LUMA_IN2CSC_OFFSET: Offset values for Y before and after matrix multiplication for input color space conversion
V_BLEND_CR_IN2CSC_OFFSET0x0000A0A832mixed0x00000000V_BLEND_CR_IN2CSC_OFFSET: Offset values for CR before and after matrix multiplication for input color space conversion
V_BLEND_CB_IN2CSC_OFFSET0x0000A0AC32mixed0x00000000V_BLEND_CB_IN2CSC_OFFSET: Offset values for CB before and after matrix multiplication for input color space conversion
V_BLEND_CHROMA_KEY_ENABLE0x0000A1D032mixed0x00000000V_BLEND_CHROMA_KEY_ENABLE
V_BLEND_CHROMA_KEY_COMP10x0000A1D432mixed0x00000000V_BLEND_CHROMA_KEY_COMP1:
V_BLEND_CHROMA_KEY_COMP20x0000A1D832mixed0x00000000V_BLEND_CHROMA_KEY_COMP2
V_BLEND_CHROMA_KEY_COMP30x0000A1DC32mixed0x00000000V_BLEND_CHROMA_KEY_COMP3: [11:0]: B component of the key minimum value [27:16]: B component of the key maximum value
AV_BUF_FORMAT0x0000B00032mixed0x00000000AV_BUF_FORMAT: This register should be programmed based on the Video/Graphics packing format in memory. DP unpacker works based on this
AV_BUF_NON_LIVE_LATENCY0x0000B00832mixed0x00000180The memory fetch latency. This parameter is used to offset the early VTC. The max latency supported is 412. This should have a buffer of 35 pixel clocks than actual maximum latency expected in the system
AV_CHBUF00x0000B01032mixed0x00000000AV_CHBUF0: Channel Enable, flush and Burst length to be programmed based on video formats. Each channel can be programmed with independent BL Channel
0: must be always enabled for any video mode. Channel 1 and
2: should be enabled for planar modes. Channel
3: for graphics. Channel 4 and
5: for audio modes
AV_CHBUF10x0000B01432mixed0x00000000AV_CHBUF1:Same as AV_CHBUF0
AV_CHBUF20x0000B01832mixed0x00000000AV_CHBUF2:Same as AV_CHBUF0
AV_CHBUF30x0000B01C32mixed0x00000000AV_CHBUF3:Same as AV_CHBUF0
AV_CHBUF40x0000B02032mixed0x00000000AV_CHBUF4
AV_CHBUF50x0000B02432mixed0x00000000AV_CHBUF5: Same as AV_CHBUF4
AV_BUF_STC_CONTROL0x0000B02C32rw0x00000000AV_BUF_STC_CONTROL:
AV_BUF_STC_INIT_VALUE00x0000B03032rw0x00000000AV_BUF_STC_INIT_VALUE0:
AV_BUF_STC_INIT_VALUE10x0000B03432mixed0x00000000AV_BUF_STC_INIT_VALUE1:
AV_BUF_STC_ADJ0x0000B03832rw0x00000000AV_BUF_STC_ADJ: A write to this register triggers STC adjust
AV_BUF_STC_VIDEO_VSYNC_TS_REG00x0000B03C32ro0x00000000AV_BUF_STC_VIDEO_VSYNC_TS_REG0: STC TS with VSYNC event
AV_BUF_STC_VIDEO_VSYNC_TS_REG10x0000B04032mixed0x00000000AV_BUF_STC_VIDEO_VSYNC_TS_REG1: STC TS with VSYNC event
AV_BUF_STC_EXT_VSYNC_TS_REG00x0000B04432ro0x00000000AV_BUF_STC_EXT_VSYNC_TS_REG0: STC TS with external VSYNC event
AV_BUF_STC_EXT_VSYNC_TS_REG10x0000B04832mixed0x00000000AV_BUF_STC_EXT_VSYNC_TS_REG1: STC TS with VSYNC event
AV_BUF_STC_CUSTOM_EVENT_TS_REG00x0000B04C32ro0x00000000AV_BUF_STC_CUSTOM_EVENT_TS_REG0: STC TS with custom event1
AV_BUF_STC_CUSTOM_EVENT_TS_REG10x0000B05032mixed0x00000000AV_BUF_STC_CUSTOM_EVENT_TS_REG1: STC TS with custom event1
AV_BUF_STC_CUSTOM_EVENT2_TS_REG00x0000B05432ro0x00000000AV_BUF_STC_CUSTOM_EVENT2_TS_REG0: STC TS with custom event 2 (can be audio TS)
AV_BUF_STC_CUSTOM_EVENT2_TS_REG10x0000B05832mixed0x00000000AV_BUF_STC_CUSTOM_EVENT2_TS_REG1: STC TS with custom event2
AV_BUF_STC_SNAPSHOT00x0000B06032ro0x00000000AV_BUF_STC_SNAPSHOT0
AV_BUF_STC_SNAPSHOT10x0000B06432mixed0x00000000AV_BUF_STC_SNAPSHOT1
AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT0x0000B07032mixed0x00000008AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT: to select the buffer manager outputs
AV_BUF_HCOUNT_VCOUNT_INT00x0000B07432rw0x00000000AV_BUF_HCOUNT_VCOUNT_INT0: When the early VTC timing values(VCOUNT and HCOUNT) match the values programmed in this register and corresponding interrupt mask is enabled, an interrupt is generated
AV_BUF_HCOUNT_VCOUNT_INT10x0000B07832rw0x00000000AV_BUF_HCOUNT_VCOUNT_INT1: When the early VTC timing values(VCOUNT and HCOUNT) match the values programmed in this register and corresponding interrupt mask is enabled, an interrupt is generated
AV_BUF_DITHER_CONFIG0x0000B07C32mixed0x00000000This register is used for configuring dither functions
DITHER_CONFIG_SEED00x0000B08032mixed0x00008000To set seed for LFSR0
DITHER_CONFIG_SEED10x0000B08432mixed0x00008080Description same as DITHER_CONFIG_SEED0
DITHER_CONFIG_SEED20x0000B08832mixed0x00008008Description same as DITHER_CONFIG_SEED0
DITHER_CONFIG_MAX0x0000B08C32mixed0x00000FFFTo set the max output value on video pixel (at the blender output towards DP )
DITHER_CONFIG_MIN0x0000B09032mixed0x00000000To set the min output value on video pixel (at the blender output towards DP )
PATTERN_GEN_SELECT0x0000B10032mixed0x00000000PATTERN_GEN_SELECT:PATTERN_GEN_SELECT:
AUD_PATTERN_SELECT10x0000B10432mixed0x00000000AUD_CH1_PAT_SELECT
AUD_PATTERN_SELECT20x0000B10832mixed0x00000000AUD_CH2_PAT_SELECT
AV_BUF_AUD_VID_CLK_SOURCE0x0000B12032mixed0x00000000AV_BUF_AUD_VID_CLK_SOURCE: When live video from PL is absent, then the internal clock shall be video pipeline clock. If the live video is present, then clock from PL shall be the video pipe line clock. Similarly for the audio we can select from either PS or PL clock
AV_BUF_SRST_REG0x0000B12432mixed0x00000000AV_BUF_SRST_REG
AV_BUF_AUDIO_RDY_INTERVAL0x0000B12832rw0x00000000AV_BUF_AUDIO_RDY_INTERVAL. Debug register.
AV_BUF_AUDIO_CH_CONFIG0x0000B12C32mixed0x00000000AV_BUF_AUDIO_CH_CONFIG
AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR0x0000B20032mixed0x00010101Scaling factor for graphics for component 0 For 4-bits, scale factor will be 16/15*2^16 = 0x11111 For 5-bits, scale factor will be 32/31*2^16 = 0x10842 For 6-bits, scale factor will be 64/63*2^16 = 0x10410. For 8-bits, scale factor will be 256/255*2^16 = 0x10101 For 10-bits, scale factor will be 1024/1023*2^16 = 0x10040 For BPC =12, no scaling is done. This register is unused and can be default
AV_BUF_GRAPHICS_COMP1_SCALE_FACTOR0x0000B20432mixed0x00010101Scaling factor for graphics for component1. Description same as AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR
AV_BUF_GRAPHICS_COMP2_SCALE_FACTOR0x0000B20832mixed0x00010101Scaling factor for graphics for component 2.Description same as AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR
AV_BUF_VIDEO_COMP0_SCALE_FACTOR0x0000B20C32mixed0x00010101Scaling factor for video color comp0.Description same as AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR
AV_BUF_VIDEO_COMP1_SCALE_FACTOR0x0000B21032mixed0x00010101Scaling factor for video color comp1.Description same as AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR
AV_BUF_VIDEO_COMP2_SCALE_FACTOR0x0000B21432mixed0x00010101Scaling factor for video color comp2.Description same as AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR
AV_BUF_LIVE_VIDEO_COMP0_SF0x0000B21832mixed0x00010101Scaling factor for live video color comp0.Description same as AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR
AV_BUF_LIVE_VIDEO_COMP1_SF0x0000B21C32mixed0x00010101Scaling factor for live video color comp1.Description same as AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR
AV_BUF_LIVE_VIDEO_COMP2_SF0x0000B22032mixed0x00010101Scaling factor for live video color comp2.Description same as AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR
AV_BUF_LIVE_VID_CONFIG0x0000B22432mixed0x00000000Programmable option to configure Cb or Cr first, when YUV422 mode is enabled
AV_BUF_LIVE_GFX_COMP0_SF0x0000B22832mixed0x00010101Scaling factor for live graphics color comp0.Description same as AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR
AV_BUF_LIVE_GFX_COMP1_SF0x0000B22C32mixed0x00010101Scaling factor for live graphics color comp1.Description same as AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR
AV_BUF_LIVE_GFX_COMP2_SF0x0000B23032mixed0x00010101Scaling factor for live graphics color comp2.Description same as AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR
AV_BUF_LIVE_GFX_CONFIG0x0000B23432mixed0x00000000Programmable option to configure Cb or Cr first, when YUV422 mode is enabled
AUDIO_MIXER_VOLUME_CONTROL0x0000C00032rw0x00000000AUDIO_MIXER_VOLUME_CONTROL:Setting value to 8192 means no volume change (1.0 scaling factor)
AUDIO_MIXER_META_DATA0x0000C00432mixed0x00000000AUDIO_MIXER_META_DATA
AUD_CH_STATUS_REG00x0000C00832rw0x00000000AUD_CH_STATUS_REG0: Audio Channel status bits 31 to 0
AUD_CH_STATUS_REG10x0000C00C32rw0x00000000AUD_CH_STATUS_REG1: Audio Channel status bits 63 to 32
AUD_CH_STATUS_REG20x0000C01032rw0x00000000AUD_CH_STATUS_REG2: Audio Channel status bits 95 to 64
AUD_CH_STATUS_REG30x0000C01432rw0x00000000AUD_CH_STATUS_REG3: Audio Channel status bits 127 to 96
AUD_CH_STATUS_REG40x0000C01832rw0x00000000AUD_CH_STATUS_REG4: Audio Channel status bits 159 to 128
AUD_CH_STATUS_REG50x0000C01C32rw0x00000000AUD_CH_STATUS_REG5: Audio Channel status bits 191 to 160
AUD_CH_A_DATA_REG00x0000C02032rw0x00000000AUD_CH_A_DATA_REG0: User data bits 31 to 0
AUD_CH_A_DATA_REG10x0000C02432rw0x00000000AUD_CH_A_DATA_REG1: User data bits 63 to 32
AUD_CH_A_DATA_REG20x0000C02832rw0x00000000AUD_CH_A_DATA_REG2: User data bits 95 to 64
AUD_CH_A_DATA_REG30x0000C02C32rw0x00000000AUD_CH_A_DATA_REG3: User data bits 127 to 96
AUD_CH_A_DATA_REG40x0000C03032rw0x00000000AUD_CH_A_DATA_REG4: User data bits 159 to 128
AUD_CH_A_DATA_REG50x0000C03432rw0x00000000AUD_CH_A_DATA_REG5: User data bits 191 to 160
AUD_CH_B_DATA_REG00x0000C03832rw0x00000000AUD_CH_B_DATA_REG0: User data bits 31 to 0.
AUD_CH_B_DATA_REG10x0000C03C32rw0x00000000AUD_CH_B_DATA_REG1: User data bits 63 to 32.
AUD_CH_B_DATA_REG20x0000C04032rw0x00000000AUD_CH_B_DATA_REG2: User data bits 95 to 64.
AUD_CH_B_DATA_REG30x0000C04432rw0x00000000AUD_CH_B_DATA_REG3: User data bits 127 to 96.
AUD_CH_B_DATA_REG40x0000C04832rw0x00000000AUD_CH_B_DATA_REG4: User data bits 159 to 128.
AUD_CH_B_DATA_REG50x0000C04C32rw0x00000000AUD_CH_B_DATA_REG5: User data bits 191 to 160.
AUDIO_SOFT_RESET0x0000CC0032mixed0x00000000Audio Soft reset reigster.
PATGEN_CRC_R0x0000CC1032mixed0x0000000016 bit CRC calculated on the first component of video output from Internal Test Pattern Generator
PATGEN_CRC_G0x0000CC1432mixed0x0000000016 bit CRC calculated on the second component of video output from Internal Test Pattern Generator
PATGEN_CRC_B0x0000CC1832mixed0x0000000016 bit CRC calculated on the third component of video output from Internal Test Pattern Generator