Register Name | Offset Address | Width | Type | Reset Value | Description |
Config_reg | 0x0000000000 | 32 | mixedMixed types. See bit-field details. | 0x80000000 | QSPI configuration register |
Intr_status_REG | 0x0000000004 | 32 | mixedMixed types. See bit-field details. | 0x00000104 | Interrupt Status |
Intrpt_en_REG | 0x0000000008 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Enable |
Intrpt_dis_REG | 0x000000000C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Disable |
QSPI_Intrpt_mask_REG | 0x0000000010 | 32 | roRead-only | 0x00000000 | Interrupt Un-Mask (enabled) |
En_REG | 0x0000000014 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | LQSPI Enable |
Delay_REG | 0x0000000018 | 32 | rwNormal read/write | 0x00000000 | Timing Control Delay |
TXD0 | 0x000000001C | 32 | woWrite-only | 0x00000000 | Transmit Data, 4 Bytes |
Rx_data_REG | 0x0000000020 | 32 | roRead-only | 0x00000000 | Receive Data in RX FIFO |
Slave_Idle_count_REG | 0x0000000024 | 32 | roRead-only | 0x00000000 | Slave Idle Count |
TX_thres_REG | 0x0000000028 | 32 | rwNormal read/write | 0x00000001 | TX FIFO Threshold |
RX_thres_REG | 0x000000002C | 32 | rwNormal read/write | 0x00000001 | RX FIFO Threshold |
GPIO | 0x0000000030 | 32 | rwNormal read/write | 0x00000001 | Write Protection Output |
LPBK_DLY_ADJ | 0x0000000038 | 32 | rwNormal read/write | 0x00000033 | Loopback Master Clock Delay Adjustment |
TXD1 | 0x0000000080 | 32 | woWrite-only | 0x00000000 | Transmit Data, 1 Byte |
TXD2 | 0x0000000084 | 32 | woWrite-only | 0x00000000 | Transmit Data, 2 Byte |
TXD3 | 0x0000000088 | 32 | woWrite-only | 0x00000000 | Transmit Data, 3 Bytes |
LQSPI_CFG | 0x00000000A0 | 32 | rwNormal read/write | 0x000002EB | Configuration |
LQSPI_STS | 0x00000000A4 | 9 | roRead-only | 0x00000000 | Status |
CMND_REG | 0x00000000C0 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Command control |
TRANSFER_SIZE | 0x00000000C4 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Transfer Size |
DUMMY_CYCLE_EN | 0x00000000C8 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Dummy Cycles Enable |
MOD_ID | 0x00000000FC | 32 | rwNormal read/write | 0x01090101 | Module Identification |
GQSPI_CFG | 0x0000000100 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | GQSPI Configuration |
GQSPI_ISR | 0x0000000104 | 32 | mixedMixed types. See bit-field details. | 0x00000B84 | Generic QSPI Interrupt Status |
GQSPI_IER | 0x0000000108 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | GQSPI Interrupt Enable |
GQSPI_IDR | 0x000000010C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | GQSPI Interrupt disable |
GQSPI_IMASK | 0x0000000110 | 32 | mixedMixed types. See bit-field details. | 0x00000FBE | GQSPI Interrupt Mask |
GQSPI_En_REG | 0x0000000114 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | GQSPI_Enable |
GQSPI_TXD | 0x000000011C | 32 | woWrite-only | 0x00000000 | GQSPI Transmit Data |
GQSPI_RXD | 0x0000000120 | 32 | roRead-only | 0x00000000 | GQSPI Receive Data |
GQSPI_TX_THRESH | 0x0000000128 | 32 | mixedMixed types. See bit-field details. | 0x00000001 | GQSPI TX FIFO Threshold Level |
GQSPI_RX_THRESH | 0x000000012C | 32 | mixedMixed types. See bit-field details. | 0x00000001 | GQSPI RX FIFO Threshold Level |
GQSPI_GPIO | 0x0000000130 | 32 | rwNormal read/write | 0x00000001 | GQSPI GPIO for Write Protect |
GQSPI_LPBK_DLY_ADJ | 0x0000000138 | 32 | mixedMixed types. See bit-field details. | 0x00000033 | GQSPI Loopback clock delay adjustment Register |
GQSPI_GEN_FIFO | 0x0000000140 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | GQSPI Generic FIFO Configuration |
GQSPI_SEL | 0x0000000144 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | GQSPI Select |
GQSPI_FIFO_CTRL | 0x000000014C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | GQSPI FIFO Control |
GQSPI_GF_THRESH | 0x0000000150 | 32 | mixedMixed types. See bit-field details. | 0x00000010 | GQSPI Generic FIFO Threshold Level |
GQSPI_POLL_CFG | 0x0000000154 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | GQSPI Poll Configuration Register |
GQSPI_P_TIMEOUT | 0x0000000158 | 32 | rwNormal read/write | 0x00000000 | GQSPI Poll Time out |
QSPI_DATA_DLY_ADJ | 0x00000001F8 | 32 | rwNormal read/write | 0x00000000 | QSPI RX Data Delay |
GQSPI_MOD_ID | 0x00000001FC | 32 | rwNormal read/write | 0x010A0000 | GQSPI Module Identification register |
QSPIDMA_DST_ADDR | 0x0000000800 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | DMA destination memory address |
QSPIDMA_DST_SIZE | 0x0000000804 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | DMA transfer payload |
QSPIDMA_DST_STS | 0x0000000808 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | General DST DMA Status |
QSPIDMA_DST_CTRL | 0x000000080C | 32 | rwNormal read/write | 0x803FFA00 | General DST DMA Control |
QSPIDMA_DST_I_STS | 0x0000000814 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | DST DMA Interrupt Status |
QSPIDMA_DST_I_EN | 0x0000000818 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | DST DMA Interrupt Enable |
QSPIDMA_DST_I_DIS | 0x000000081C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | DST DMA Interrupt Disable |
QSPIDMA_DST_I_MASK | 0x0000000820 | 32 | mixedMixed types. See bit-field details. | 0x000000FE | DST DMA Interrupt Mask |
QSPIDMA_DST_CTRL2 | 0x0000000824 | 32 | mixedMixed types. See bit-field details. | 0x0000FFF8 | General DST DMA Control Reg 2 |
QSPIDMA_DST_ADDR_MSB | 0x0000000828 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | DMA destination memory address (MSBs) |