Zynq UltraScale+ Devices Register Reference > Module Summary > QSPI Module

QSPI Module

QSPI Module Description

Module NameQuad SPI Registers (QSPI)
Modules of this TypeQSPI
Base Address0xFF0F0000 (QSPI)
DescriptionQuad SPI Controller

QSPI Module Register Summary

Register NameAddressWidthTypeReset ValueDescription
Config0x0000000032mixed0x80000000QSPI configuration register
ISR0x0000000432mixed0x00000104Interrupt Status
IER0x0000000832mixed0x00000000Interrupt Enable
IDR0x0000000C32mixed0x00000000Interrupt Disable
IMR0x0000001032ro0x00000000Interrupt Un-Mask (enabled)
LQSPI_En0x0000001432mixed0x00000000LQSPI Enable
Delay0x0000001832rw0x00000000Timing Control Delay
TXD00x0000001C32wo0x00000000Transmit Data, 4 Bytes
Rx_data0x0000002032ro0x00000000Receive Data in RX FIFO
Slave_Idle_count0x0000002432mixed0x000000FFSlave Idle Count
TX_thres0x0000002832rw0x00000001TX FIFO Threshold
RX_thres0x0000002C32rw0x00000001RX FIFO Threshold
GPIO0x0000003032rw0x00000001Write Protection Output
LPBK_DLY_ADJ0x0000003832rw0x00000033Loopback Master Clock Delay Adjustment
TXD10x0000008032wo0x00000000Transmit Data, 1 Byte
TXD20x0000008432wo0x00000000Transmit Data, 2 Byte
TXD30x0000008832wo0x00000000Transmit Data, 3 Bytes
LQSPI_CFG0x000000A032rw0x000002EBConfiguration
LQSPI_STS0x000000A4 9ro0x00000000Status
COMMAND0x000000C032mixed0x00000000Command control
TRANSFER_SIZE0x000000C432mixed0x00000000Transfer Size
DUMMY_CYCLE_EN0x000000C832mixed0x00000000Dummy Cycles Enable
MOD_ID0x000000FC32rw0x01090101Module Identification
GQSPI_CFG0x0000010032mixed0x00000000GQSPI Configuration
GQSPI_ISR0x0000010432mixed0x00000B84Generic QSPI Interrupt Status
GQSPI_IER0x0000010832mixed0x00000000GQSPI Interrupt Enable
GQSPI_IDR0x0000010C32mixed0x00000000GQSPI Interrupt disable
GQSPI_IMR0x0000011032mixed0x00000FBEGQSPI Interrupt Mask
GQSPI_En0x0000011432mixed0x00000000GQSPI_Enable
GQSPI_TXD0x0000011C32wo0x00000000GQSPI Transmit Data
GQSPI_RXD0x0000012032ro0x00000000GQSPI Receive Data
GQSPI_TX_THRESH0x0000012832mixed0x00000001GQSPI TX FIFO Threshold Level
GQSPI_RX_THRESH0x0000012C32mixed0x00000001GQSPI RX FIFO Threshold Level
GQSPI_GPIO0x0000013032mixed0x00000001GQSPI GPIO for Write Protect
GQSPI_LPBK_DLY_ADJ0x0000013832mixed0x00000033GQSPI Loopback clock delay adjustment Register
GQSPI_GEN_FIFO0x0000014032mixed0x00000000GQSPI Generic FIFO Configuration
GQSPI_SEL0x0000014432mixed0x00000000GQSPI Select
GQSPI_FIFO_CTRL0x0000014C32mixed0x00000000GQSPI FIFO Control
GQSPI_GF_THRESH0x0000015032mixed0x00000010GQSPI Generic FIFO Threshold Level
GQSPI_POLL_CFG0x0000015432mixed0x00000000GQSPI Poll Configuration Register
GQSPI_P_TIMEOUT0x0000015832rw0x00000000GQSPI Poll Time out
QSPI_DATA_DLY_ADJ0x000001F832rw0x00000000QSPI RX Data Delay
GQSPI_MOD_ID0x000001FC32rw0x010A0000GQSPI Module Identification register
QSPIDMA_DST_ADDR0x0000080032mixed0x00000000DMA destination memory address
QSPIDMA_DST_SIZE0x0000080432mixed0x00000000DMA transfer payload
QSPIDMA_DST_STS0x0000080832mixed0x00000000General DST DMA Status
QSPIDMA_DST_CTRL0x0000080C32rw0x803FFA00General DST DMA Control
QSPIDMA_DST_I_STS0x0000081432mixed0x00000000DST DMA Interrupt Status
QSPIDMA_DST_I_EN0x0000081832mixed0x00000000DST DMA Interrupt Enable
QSPIDMA_DST_I_DIS0x0000081C32mixed0x00000000DST DMA Interrupt Disable
QSPIDMA_DST_I_MASK0x0000082032mixed0x000000FEDST DMA Interrupt Mask
QSPIDMA_DST_CTRL20x0000082432mixed0x081BFFF8General DST DMA Control Reg 2
QSPIDMA_DST_ADDR_MSB0x0000082832mixed0x00000000DMA destination memory address (MSBs)