QSPI Module

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

QSPI Module Description

Module NameQSPI Module
Modules of this TypeQSPI
Base Addresses 0x00FF0F0000 (QSPI)
DescriptionQuad-SPI Registers

QSPI Module Register Summary

Register NameOffset AddressWidthTypeReset ValueDescription
Config_reg0x000000000032mixedMixed types. See bit-field details.0x80000000QSPI configuration register
Intr_status_REG0x000000000432mixedMixed types. See bit-field details.0x00000104Interrupt Status
Intrpt_en_REG0x000000000832mixedMixed types. See bit-field details.0x00000000Interrupt Enable
Intrpt_dis_REG0x000000000C32mixedMixed types. See bit-field details.0x00000000Interrupt Disable
QSPI_Intrpt_mask_REG0x000000001032roRead-only0x00000000Interrupt Un-Mask (enabled)
En_REG0x000000001432mixedMixed types. See bit-field details.0x00000000LQSPI Enable
Delay_REG0x000000001832rwNormal read/write0x00000000Timing Control Delay
TXD00x000000001C32woWrite-only0x00000000Transmit Data, 4 Bytes
Rx_data_REG0x000000002032roRead-only0x00000000Receive Data in RX FIFO
Slave_Idle_count_REG0x000000002432roRead-only0x00000000Slave Idle Count
TX_thres_REG0x000000002832rwNormal read/write0x00000001TX FIFO Threshold
RX_thres_REG0x000000002C32rwNormal read/write0x00000001RX FIFO Threshold
GPIO0x000000003032rwNormal read/write0x00000001Write Protection Output
LPBK_DLY_ADJ0x000000003832rwNormal read/write0x00000033Loopback Master Clock Delay Adjustment
TXD10x000000008032woWrite-only0x00000000Transmit Data, 1 Byte
TXD20x000000008432woWrite-only0x00000000Transmit Data, 2 Byte
TXD30x000000008832woWrite-only0x00000000Transmit Data, 3 Bytes
LQSPI_CFG0x00000000A032rwNormal read/write0x000002EBConfiguration
LQSPI_STS0x00000000A4 9roRead-only0x00000000Status
CMND_REG0x00000000C032mixedMixed types. See bit-field details.0x00000000Command control
TRANSFER_SIZE0x00000000C432mixedMixed types. See bit-field details.0x00000000Transfer Size
DUMMY_CYCLE_EN0x00000000C832mixedMixed types. See bit-field details.0x00000000Dummy Cycles Enable
MOD_ID0x00000000FC32rwNormal read/write0x01090101Module Identification
GQSPI_CFG0x000000010032mixedMixed types. See bit-field details.0x00000000GQSPI Configuration
GQSPI_ISR0x000000010432mixedMixed types. See bit-field details.0x00000B84Generic QSPI Interrupt Status
GQSPI_IER0x000000010832mixedMixed types. See bit-field details.0x00000000GQSPI Interrupt Enable
GQSPI_IDR0x000000010C32mixedMixed types. See bit-field details.0x00000000GQSPI Interrupt disable
GQSPI_IMASK0x000000011032mixedMixed types. See bit-field details.0x00000FBEGQSPI Interrupt Mask
GQSPI_En_REG0x000000011432mixedMixed types. See bit-field details.0x00000000GQSPI_Enable
GQSPI_TXD0x000000011C32woWrite-only0x00000000GQSPI Transmit Data
GQSPI_RXD0x000000012032roRead-only0x00000000GQSPI Receive Data
GQSPI_TX_THRESH0x000000012832mixedMixed types. See bit-field details.0x00000001GQSPI TX FIFO Threshold Level
GQSPI_RX_THRESH0x000000012C32mixedMixed types. See bit-field details.0x00000001GQSPI RX FIFO Threshold Level
GQSPI_GPIO0x000000013032rwNormal read/write0x00000001GQSPI GPIO for Write Protect
GQSPI_LPBK_DLY_ADJ0x000000013832mixedMixed types. See bit-field details.0x00000033GQSPI Loopback clock delay adjustment Register
GQSPI_GEN_FIFO0x000000014032mixedMixed types. See bit-field details.0x00000000GQSPI Generic FIFO Configuration
GQSPI_SEL0x000000014432mixedMixed types. See bit-field details.0x00000000GQSPI Select
GQSPI_FIFO_CTRL0x000000014C32mixedMixed types. See bit-field details.0x00000000GQSPI FIFO Control
GQSPI_GF_THRESH0x000000015032mixedMixed types. See bit-field details.0x00000010GQSPI Generic FIFO Threshold
Level
GQSPI_POLL_CFG0x000000015432mixedMixed types. See bit-field details.0x00000000GQSPI Poll Configuration Register
GQSPI_P_TIMEOUT0x000000015832rwNormal read/write0x00000000GQSPI Poll Time out
QSPI_DATA_DLY_ADJ0x00000001F832rwNormal read/write0x00000000QSPI RX Data Delay
GQSPI_MOD_ID0x00000001FC32rwNormal read/write0x010A0000GQSPI Module Identification register
QSPIDMA_DST_ADDR0x000000080032mixedMixed types. See bit-field details.0x00000000DMA destination memory address
QSPIDMA_DST_SIZE0x000000080432mixedMixed types. See bit-field details.0x00000000DMA transfer payload
QSPIDMA_DST_STS0x000000080832mixedMixed types. See bit-field details.0x00000000General DST DMA Status
QSPIDMA_DST_CTRL0x000000080C32rwNormal read/write0x803FFA00General DST DMA Control
QSPIDMA_DST_I_STS0x000000081432mixedMixed types. See bit-field details.0x00000000DST DMA Interrupt Status
QSPIDMA_DST_I_EN0x000000081832mixedMixed types. See bit-field details.0x00000000DST DMA Interrupt Enable
QSPIDMA_DST_I_DIS0x000000081C32mixedMixed types. See bit-field details.0x00000000DST DMA Interrupt Disable
QSPIDMA_DST_I_MASK0x000000082032mixedMixed types. See bit-field details.0x000000FEDST DMA Interrupt Mask
QSPIDMA_DST_CTRL20x000000082432mixedMixed types. See bit-field details.0x0000FFF8General DST DMA Control Reg 2
QSPIDMA_DST_ADDR_MSB0x000000082832mixedMixed types. See bit-field details.0x00000000DMA destination memory address (MSBs)