GFLADJ (USB3_XHCI) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

GFLADJ (USB3_XHCI) Register Description

Register NameGFLADJ
Offset Address0x000000C630
Absolute Address 0x00FE20C630 (USB3_0_XHCI)
0x00FE30C630 (USB3_1_XHCI)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionGlobal Frame Length Adjustment Register
This register provides options for the software to control the core behavior with respect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an option to override the fladj_30mhz_reg sideband signal. In addition, it enables running SOF or ITP frame timer counters completely from the ref_clk. This facilitates hardware LPM in host mode with the SOF or ITP counters being run from the ref_clk signal.

GFLADJ (USB3_XHCI) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
GFLADJ_REFCLK_240MHZDECR_PLS131rwNormal read/write0GFLADJ_REFCLK_240MHZDECR_PLS1
This field indicates that the decrement value that the controller applies for each ref_clk
must be GFLADJ_REFCLK_240MHZ_DECR and GFLADJ_REFCLK_240MHZ_DECR +1 alternatively on each ref_clk.
Set this bit to a 1 only if GFLADJ_REFCLK_LPM_SEL is set to 1 and the fractional component of 240/ref_frequency is greater than or equal to 0.5.
Examples:
If the ref_clk is 19.2 MHz then
- GUCTL.REF_CLK_PERIOD = 52
- GFLADJ.GFLADJ_REFCLK_240MHZ_DECR = (240/19.2) = 12.5
- GFLADJ.GFLADJ_REFCLK_240MHZDECR_PLS1 = 1
If the ref_clk is 24 MHz then
- GUCTL.REF_CLK_PERIOD = 41
- GFLADJ.GFLADJ_REFCLK_240MHZ_DECR = (240/24) = 10
- GFLADJ.GFLADJ_REFCLK_240MHZDECR_PLS1 = 0
GFLADJ_REFCLK_240MHZ_DECR30:24rwNormal read/write0This field indicates the decrement value that the controller applies for each ref_clk in order to derive a frame timer in terms of a 240-MHz clock.
This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to 1.
The value is derived as follows:
GFLADJ_REFCLK_240MHZ_DECR = 240/ref_clk_frequency
Examples:
If the ref_clk is 24 MHz then
- GUCTL.REF_CLK_PERIOD = 41
- GFLADJ.GFLADJ_REFCLK_240MHZ_DECR = 240/24 = 10
If the ref_clk is 48 MHz then
- GUCTL.REF_CLK_PERIOD = 20
- GFLADJ.GFLADJ_REFCLK_240MHZ_DECR = 240/48 = 5
If the ref_clk is 17 MHz then
- GUCTL.REF_CLK_PERIOD = 58
- GFLADJ.GFLADJ_REFCLK_240MHZ_DECR = 240/17 = 14
GFLADJ_REFCLK_LPM_SEL23rwNormal read/write0This bit enables the functionality of running SOF/ITP counters on the ref_clk.
This bit must not be set to 1 if GCTL.SOFITPSYNC bit is set to 1.
Similarly, if GFLADJ_REFCLK_LPM_SEL set to 1, GCTL.SOFITPSYNC must not be set to 1.
When GFLADJ_REFCLK_LPM_SEL is set to 1 the overloading of the suspend control of the USB 2.0 first port PHY (UTMI/ULPI) with USB 3.0 port states is removed.
For example, for
PHY, the COMMONONN signal can be tied to 1.
Note that the ref_clk frequencies supported in this mode are 16/17/19.2/20/24/39.7/40 MHz. The utmi_clk[0] signal of the core must be connected to the FREECLK of the PHY.
Note: If you set this bit to 1, the GUSB2PHYCFG.U2_FREECLK_EXISTS bit must be set to 0.
Reserved22roRead-only0x0Reserved for future use
GFLADJ_REFCLK_FLADJ21:8rwNormal read/write0This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk.
This register value is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to 1; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LPM_SEL is set to 1.
This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to 1 or GCTL.SOFITPSYNC is set to 1.
The value is derived as follows:
FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_period)) * ref_clk_period
where
- the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the decimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field.
- the ref_clk_period is the ref_clk period including the fractional value.
Examples:
If the ref_clk is 24 MHz then
- GUCTL.REF_CLK_PERIOD = 41
- GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value)
If the ref_clk is 48 MHz then
- GUCTL.REF_CLK_PERIOD = 20
- GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)
GFLADJ_30MHZ_SDBND_SEL 7rwNormal read/write0GFLADJ_30MHZ_SDBND_SEL
This field selects whether to use the input signal fladj_30mhz_reg or the GFLADJ.GFLADJ_30MHZ to adjust the frame length for the SOF/ITP.
When this bit is set to,
- 1, the controller uses the register field GFLADJ.GFLADJ_30MHZ value
- 0, the controller uses the input signal fladj_30mhz_reg value
Reserved 6roRead-only0x0Reserved for future use
GFLADJ_30MHZ 5:0rwNormal read/write0GFLADJ_30MHZ
This field indicates the value that is used for frame length adjustment instead of considering from the sideband input signal fladj_30mhz_reg.
This enables post-silicon frame length adjustment in case the input signal fladj_30mhz_reg is connected to a wrong value or is not valid.
For details on how to set this value, refer to section 5.2.4, Frame Length Adjustment Register (FLADJ), of the
xHCI Specification.