GUCTL (USB3_XHCI) Register Description
| Register Name | GUCTL |
|---|---|
| Offset Address | 0x000000C12C |
| Absolute Address |
0x00FE20C12C (USB3_0_XHCI) 0x00FE30C12C (USB3_1_XHCI) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Global User Control Register: This register provides a few options for the software to control the core behavior in the Host mode. Most of the options are used to improve host inter-operability with different devices. |
GUCTL (USB3_XHCI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| REFCLKPER | 31:22 | rwNormal read/write | 0 | REFCLKPER This field indicates in terms of nano seconds the period of ref_clk. The default value of this register is set to h8 (8ns/125 MHz). This field needs to be updated during power-on initialization, if GCTL.SOFITPSYNC or GFLADJ.GFLADJ_REFCLK_LPM_SEL is set to 1. The programmable maximum value is 62ns, and the minimum value is 8ns. You must use a reference clock with a period that is an integer multiple, so that ITP can meet the jitter margin of 32ns. The allowable ref_clk frequencies whose period is not integer multiples are 16/17/19.2/24/39.7MHz. This field must not be set to 0 at any time. If you never plan to use this feature, then set this field to h8, the default value. |
| NoExtrDl | 21 | rwNormal read/write | 0 | No Extra Delay Between SOF and the First Packet(NoExtrDl) Some HS devices misbehave when the host sends a packet immediately after a SOF. However, adding an extra delay between a SOF and the first packet can reduce the USB data rate and performance. This bit is used to control whether the host must wait for 2 microseconds before it sends the first packet after a SOF, or not. User can set this bit to one to improve the performance if those problematic devices are not a concern in the users host environment. - 1b0: Host waits for 2 microseconds after a SOF before it sends the first USB packet. - 1b1: Host doesnt wait after a SOF before it sends the first USB packet. |
| Reserved | 20:18 | roRead-only | 0x0 | Reserved |
| SprsCtrlTransEn | 17 | rwNormal read/write | 0 | Sparse Control Transaction Enable Some devices are slow in responding to Control transfers. Scheduling multiple transactions in one microframe/frame can cause these devices to misbehave. If this bit is set to 1b1, the host controller schedules transactions for a Control transfer in different microframes/frames. |
| ResBwHSEPS | 16 | rwNormal read/write | 0 | Reserving 85% Bandwidth for HS Periodic EPs (ResBwHSEPS) By default, HC reserves 80% of the bandwidth for periodic EPs. If this bit is set, the bandwidth is relaxed to 85% to accommodate two high speed, high bandwidth ISOC EPs. USB 2.0 required 80% bandwidth allocated for ISOC traffic. If two High-bandwidth ISOC devices (HD Webcams) are connected, and if each requires 1024-bytes X 3 packets per Micro-Frame, then the bandwidth required is around 82%. If this bit is set, then it is possible to connect two Webcams of 1024bytes X 3 paylod per Micro-Frame each. Otherwise, you may have to reduce the resolution of the Webcams. This bit is valid in Host and DRD configuration and is used in host mode operation only. Ignore this bit in device mode. |
| CMdevAddr | 15 | rwNormal read/write | 0 | Compliance Mode for Device Address (CMdevAddr) When this bit is 1b1, Slot ID may have different value than Device Address if max_slot_enabled < 128. - 1b1: Increment Device Address on each Address Device command. - 1b0: Device Address is equal to Slot ID. The xHCI compliance requires this bit to be set to 1. The 0 mode is for debug purpose only. This allows you to easily identify a device connected to a port in the Lecroy or Eliisys trace during hardware debug. This bit is valid in Host and DRD configuration and is used in host mode operation only. Ignore this bit in device mode. |
| USBHstInAutoRetryEn | 14 | rwNormal read/write | 0 | Host IN Auto Retry (USBHstInAutoRetryEn) When set, this field enables the Auto Retry feature. For IN transfers (non-isochronous) that encounter data packets with CRC errors or internal overrun scenarios, the auto retry feature causes the Host core to reply to the device with a non-terminating retry ACK (that is, an ACK transaction packet with Retry = 1 and NumP != 0). If the Auto Retry feature is disabled (default), the core will respond with a terminating retry ACK (that is, an ACK transaction packet with Retry = 1 and NumP = 0). - 1b0: Auto Retry Disabled - 1b1: Auto Retry Enabled Note: This bit is also applicable to the device mode. |
| EnOverlapChk | 13 | rwNormal read/write | 0 | Enable Check for LFPS Overlap During Remote Ux Exit: If this bit is set to, - 1b1: The SuperSpeed link when exiting U1/U2/U3 waits for either the remote link LFPS or TS1/TS2 training symbols before it confirms that the LFPS handshake is complete. This is done to handle the case where the LFPS glitch causes the link to start exiting from the low power state. Looking for the LFPS overlap makes sure that the link partner also sees the LFPS. - 1b0: When the link exists U1/U2/U3 because of a remote exit, it does not look for an LFPS overlap. |
| ExtCapSupptEN | 12 | rwNormal read/write | 0 | External Extended Capability Support Enable (ExtCapSuptEN) When set, this field enables extended capabilities to be implemented outside the core. When the ExtCapSupEN is set and the Debug Capability is enabled, the Next Capability pointer in Debug Capability returns 16. A read to the first DWORD of the last internal extended capability (the xHCI Supported Protocol Capability for USB 3.0 when the Debug Capability is not enabled) returns a value of 4 in the Next Capability Pointer field. This indicates to software that there is another capability four DWORDs after this capability (for example, at address N+16 where N is the address of this DWORD). If enabled, an external address decoder that snoops the xHC slave interface must be implemented. If it sees an access to N+16 or greater, the slave access is re-routed to a piece of hardware which returns the external capability pointer register of the new capability and also handles reads/writes to this new capability and the side effects. If disabled, a read to the first DWORD of the last internal extended capability returns 0 in the Next Capability Pointer field. This indicates there are no more capabilities. |
| InsrtExtrFSBODI | 11 | rwNormal read/write | 0 | Insert Extra Delay Between FS Bulk OUT Transactions (InsrtExtrFSBODl). Some FS devices are slow to receive Bulk OUT data and can get stuck when there are consecutive Bulk OUT transactions with short inter-transaction delays. This bit is used to control whether the host inserts extra delay between consecutive Bulk OUT transactions to a FS Endpoint. - 1b0: Host doesnt insert extra delay between consecutive Bulk OUT transactions to a FS Endpoint. - 1b1: Host inserts about 12us extra delay between consecutive Bulk OUT transactions to a FS Endpoint to work around the device issue. Note: Setting this bit to one will reduce the Bulk OUT transfer performance for most of the FS devices. |
| DTCT | 10:9 | rwNormal read/write | 0 | Device Timeout Coarse Tuning (DTCT) This field is a Host mode parameter which determines how long the host waits for a response from device before considering a timeout. The core first checks the DTCT value. If it is 0, then the timeout value is defined by the DTFT. If it is non-zero, then it uses the following timeout values: - 2b00: 0 usec -> use DTFT value instead - 2b01: 500 usec - 2b10: 1.5 msec - 2b11: 6.5 msec |
| DTFT | 8:0 | rwNormal read/write | 0 | Device Timeout Fine Tuning (DTFT) This field is a Host mode parameter which determines how long the host waits for a response from device before considering a timeout. For the DTFT field to take effect, DTCT must be set to 2b00. The DTFT value is the number of 125 MHz clocks * 256 to count before considering a device timeout. The minimum value of DTFT is 2. For example, if the mac3_clk is 125 MHz clk (8 ns period), this is calculated as follows: (DTFT value) * 256 * (8 ns) Quick Reference: - if DTFT = 0x2, 2*256*8 = 4usec timeout - if DTFT = 0x5, 5*256*8 = 10usec timeout - if DTFT = 0xA, 10*256*8 = 20usec timeout - if DTFT = 0x10, 16*256*8 = 32usec timeout - if DTFT = 0x19, 25*256*8 = 51usec timeout - if DTFT = 0x31, 49*256*8 = 100usec timeout - if DTFT = 0x62, 98*256*8 = 200usec timeout Note: When SSIC is enabled, in HS_G1_G2_G3 mode when ssic_soc_pa_clk_freq = 2b01, then DTFT value must be calculated for 156.25 MHz clock, for example, for equivalent delay of 32usec DTFT value must be 9h14. |