Customizing and Generating the Core in MPSoC

Add DPU IP into Repository or Upgrade DPU from a Previous Version

In the Vivado Integrated Design Environment (IDE), click Project Manager > IP Catalog. In the IP Catalog tab, right-click and select Add Repository (see figure below), then select the location of the DPU IP.

Figure 1: Add Repository

The DPU IP will appear in the IP Catalog page.

Figure 2: DPU IP in Repository

If there is an existing hardware project with an old version of the DPU, upgrading to the latest version is required, follow these steps:

  1. Delete the old DPU IP in the block design and IP repository.
  2. Add the new DPU IP into the IP repository.
  3. Add the new DPU IP into the block design.

Add DPU IP into Block Design

Search for DPU in the block design interface and add the DPU IP into the block design. The procedure is shown in the following figures.

Figure 3: Search DPU IP
Figure 4: DPU IP into Block Design

Configure DPU Parameters

You can configure the DPU IP as shown in the following figure. Details about these parameters can be found in the DPU Configuration section.

Figure 5: Configure DPU

Connecting a DPU to the Processing System in the Xilinx SoC

The DPU IP contains only one slave interface. The number of DPU cores depends on the parameter DPU_NUM. Each DPU core has three master interfaces, one for instruction fetch, and the other two for data access.

The DPU IP can be connected to the processing system (PS) with an AXI Interconnection IP as long as the DPU can correctly access the DDR memory space. Generally, when data is transferred through an Interconnect IP, the data transaction delay will increase. The delay incurred by the Interconnect will reduce the DPU performance. Therefore, Xilinx recommends that each master interface in the DPU is connected to the PS through a direct connection rather than through an AXI Interconnect IP when the AXI slave ports of the PS are enough.

When the AXI slave ports of the PS are insufficient for the DPU, an AXI interconnect for connection is unavoidable. The two AXI master ports for data fetching are high bandwidth ports and the AXI master port for instruction fetching is a low bandwidth port. Typically, it is recommended that all the master ports for instruction fetching connect to the S_AXI_LPD of PS through one interconnect. The rest of the master ports for data fetching should be directly connected to the PS as much as possible. Xilinx recommends that the master ports of the DPU core with higher priority (smaller number, like DPU0) be directly connected to the slave ports of the PS with higher priority (smaller number, like S_AXI_HP0_FPD).

For example, if there are three DPU cores and one SFM core, there will be seven master ports, and four slave ports: S_AXI_HP1~3 and S_AXI_HPC0. A possible connection setup would be:

  • DPU0_DATA0 to HP1
  • DPU0_DATA1 to HP2
  • DPU1_DATA0 and DPU1_DATA1 to HP3
  • DPU2_DATA0, DPU2_DATA1, and SFM to HPC0

Xilinx recommends that the slave port of DPU be connected to M_AXI_HPM0_LPD of the PS.

A reference connection between the DPU and PS in the Xilinx UltraScale+™ MPSoC is shown here. The number of DPU core is set to three, and the Softmax function is enabled.

Figure 6: DPU and PS Connections for MPSoC

Assign Register Address for DPU

When the DPU connection is complete, the next step is to assign the register address of the AXI slave interface. The minimum space needed for the DPU is 16 MB. The DPU slave interface can be assigned to any starting address accessible by the host CPU.

Note: The DPU base address must be set with a range of 16 MB. The addresses in the device driver and device tree file must match those assigned in Vivado.

The reference address assignments of the DPU are shown here.

Figure 7: DPU Address Assignment

Generate Bitstream

Click Generate Bitstream in Vivado as shown below.

Figure 8: Generate Bitstream

Generate BOOT.BIN

Vivado® Design Suite or PetaLinux can be used to generate the BOOT.BIN file. For boot image creation using the Vivado Design Suite , refer to the Zynq UltraScale+ MPSoC: Embedded Design Tutorial (UG1209). For PetaLinux, refer to the PetaLinux Tools Documentation: Reference Guide (UG1144).

Device Tree

The DPU device needs to be configured correctly under the PetaLinux device tree so that the DPU driver can work properly. Create a new node for the DPU and place it as the child node of “amba” in the device tree system-user.dtsi, which is located under <plnx-proj-root>/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi. The parameters to the DPU and Softmax node are listed and described in the following table.

A device tree configuration sample for a Zynq UltraScale+ MPSoC is shown below:

&amba { 
   		...
    		dpu {    
				compatible = "xilinx,dpu";
				base-addr = <0x8f000000>;//CHANGE THIS ACCORDING TO YOUR DESIGN
				dpucore {
					compatible = "xilinx,dpucore";
					interrupt-parent = <&intc>;
					interrupts = <0x0 106 0x1 0x0 107 0x1>;
					core-num = <0x2>;
					};
        		};
				softmax {
					compatible = "xilinx, smfc";
					interrupt-parent = <&intc>;
					interrupts = <0x0 110 0x1>;
					core-num = <0x1>;
				.... 
}

The parameters are described in the following table.

Table 1. Device Tree Fields
Parameter Description
dpu Node entry for DPU device. This does not need to be modified.
dpu->compatible Fixed value set to "xilinx,dpu".
dpu->base-addr DPU base register address assigned in the hardware design.
dpucore->compatible Fixed value set to "xilinx,dpucore".
dpucore->interrupt-parent Point to interrupt control device.
Note: “intc” for Zynq-7000 devices and “gic” for Zynq UltraScale+ devices.
dpucore->interrupts Interrupt configuration for the DPU IP cores. There are three fields for each DPU core, and the second value in each field corresponds to the interrupt number. The interrupt numbers must match the hardware configuration. For the above sample, the triplet “0x0 106 0x1” is for DPU core 0 with interrupt number 106, and the triplet “0x0 107 0x1” is for DPU core 1 with interrupt number 107. The other two values in the triplet “0x0” and “0x1” are fixed values and do not need to be changed.
dpucore->core-num Number of DPU cores specified in the hardware configuration.
softmax->compatible Fixed value set to “xilinx, smfc”.
softmax->interrupt-parent

Point to interrupt control device.

Note: “intc” for Zynq-7000 devices and “gic” for Zynq UltraScale+ MPSoC devices.
softmax->interrupts Interrupt configuration for the Softmax in DPU. The second value in this field corresponds to the interrupt number. The interrupt numbers must match the hardware configuration. For the above sample, the triplet “0x0 110 0x1” is for the Softmax with interrupt number 110. The other two values in the triplet “0x0” and “0x1” are fixed values and do not need to be changed.
softmax ->core-num This value is fixed to “0x1” if softmax is added to the project in the hardware configuration.

The DPU description in the device tree should always be consistent with the configuration in the DPU hardware project, especially the interrupts. When the interrupts have been changed in the DPU project, the description in the device tree should be modified accordingly.