Customizing and Generating the Core in Zynq-7000 Devices

The latest DPU can be integrated into a Zynq®-7000 device project with some limitations:

  1. When integrating the DPU IP into a Zynq-7000 device project, a new Vivado project must be created with the target device selected as a Zynq-7000 part. Simply changing the target device of an existing Vivado project with a DPU from a Zynq® UltraScale+™ MPSoC to a Zynq-7000 will not work.
  2. The hardware softmax module is not supported in Zynq-7000 devices. The option of softmax cores is set as 0 and cannot be changed. This may change in a future release.
  3. The maximum data width of an AXI port in the processing system (PS) of the Zynq-7000 is 64 bits. The data width of the DPU will be modified from 128 bits to 64 bits. When the data width of the AXI interface is changed, the instruction file must be regenerated by the Vitis AI compiler accordingly.

The default configuration for the DPU in Zynq-7000 devices is shown below:

Figure 1: DPU Configuration in Zynq-7000 Devices