The DPU has the following features:

  • One AXI slave interface for accessing configuration and status registers.
  • One AXI master interface for accessing instructions.
  • Supports configurable AXI master interface with 64 or 128 bits for accessing data depending on the target device.
  • Supports individual configuration of each channel.
  • Supports optional interrupt request generation.
  • Some highlights of DPU functionality include:
    • Configurable hardware architecture core includes: B512, B800, B1024, B1152, B1600, B2304, B3136, and B4096
    • Maximum of four homogeneous cores
    • Convolution and deconvolution
    • Depthwise convolution
    • Max pooling
    • Average pooling
    • ReLU, ReLU6, and Leaky ReLU
    • Concat
    • Elementwise-sum
    • Dilation
    • Reorg
    • Fully connected layer
    • Softmax
    • Batch Normalization
    • Split

IP Facts

DPU IP Facts Table
Core Specifics
Supported Device Family Zynq®-7000 SoC and Zynq® UltraScale+™ MPSoC Family
Supported User Interfaces Memory-mapped AXI interfaces
Resources See DPU Configuration.
Provided with Core
Design Files Encrypted RTL
Example Design Verilog
Constraints File Xilinx Design Constraints (XDC)
Supported S/W Driver Included in PetaLinux
Tested Design Flows
Design Entry Vivado® Design Suite
Simulation N/A
Synthesis Vivado® Synthesis
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
  1. Linux OS and driver support information are available from DPU TRD or Vitis™ AI development kit.
  2. If the target device is Zynq-7000 SoC, see the notifications in Development Flow.
  3. For the supported tool versions, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).
  4. The DPU is driven by instructions generated by the Vitis AI compiler. When the target neural network (NN), DPU hardware architecture, or AXI data width is changed, the related .elf file which contains DPU instructions must be regenerated.