System Emulation

After the hardware functions are identified, the logic can be compiled into hardware and the entire system (PS and PL) verified using emulation. This provides the same level of accuracy as the final implementation without the need to compile the system into a bitstream and program the FPGA on the board.

Within the SDx Project Settings, select Generate Emulation Model to enable system emulation. Because emulation does not require a full system compile, you might be asked to disable Generate Bitstream and you are encouraged to do so to improve run time. The bitstream generation takes more time to complete than any other part of the development flow. System emulation allows you to verify and debug the system with the same level of accuracy as a full bitstream compilation.

To capture waveform data from the PL hardware emulation for viewing and debugging, select the Debug pull-down menu option. For faster emulation without capturing this hardware debug information, select the Optimized pull-down menu option. Use the Build toolbar button to compile the system for emulation after selecting Debug or Optimized mode. Once the system is compiled for emulation, the system emulator is invoked using Xilinx Tools > Start/Stop Emulator. When the Emulation window opens you can choose to run the emulation with or without waveforms.

Leaving the Show Waveform option unselected allows you to run emulation with output directed solely to the console pane. The console pane shows all system messages including the results of any print statements in the source code. Some of these statements might include the values transferred to and from the hardware functions, if desired, or simply a statement that the application has completed successfully, which would verify that the source code running on the PL and the compiled hardware functions running in the PS are functionally correct.

Selecting the Show Waveform option in the Emulation windows provides the same functionality in the console window plus an RTL waveform window. The RTL waveform window allows you to see the value of any signal in the hardware functions over time. When using this option, signals should be manually added to the waveform window before starting the emulation. Use the Scopes pane to navigate the design hierarchy, then select the signals in the Object pane you wish to monitor and use right-click to add the signals to the waveform pane. Press the Run All toolbar button to start updates to the waveform window.

Note: Running with RTL waveforms results in a slower run time, but enables detailed analysis into the operation of the hardware functions.

The system emulation is started by selecting the active project in the Project Navigator and right-clicking to select the menu options Run > Run As > Launch on the Emulator menu or Debug > Debug As > Launch on the Emulator menu. You will see the program output in the console tab, and if the Show Waveform option was selected, you will also see any appropriate response in the hardware functions in the RTL waveform. With the system emulation running, it can be paused by breakpoints in Debug mode and analysis performed in the debug perspective. During any pause in the execution of the code, the RTL waveform window continues to execute and update, just like an FPGA running on the board. The emulation can be stopped at any time using the menu option Xilinx Tools > Start/Stop Emulator and selecting Stop. For an example suitable for emulation, create a project using the Emulation Example template. The README.txt file in the project has a step-by-step guide for doing emulation on both the SDx GUI and the command line.

A system emulation session run from the command-line is shown in the following figure, with the QEMU console shown at left and the PL waveform shown on the right.