First Stage Boot Loader (FSBL)

The first stage boot loader (FSBL) is responsible for loading the bitstream and configuring the Zynq® architecture Processing System (PS) at boot time.

When the platform project is open in Vivado® Design Suite, click the File > Export > Export Hardware menu option.

Create a new software project File > New > Application Project with the name fsbl as you would using the Xilinx SDK.

Using the exported Hardware Platform, select the Zynq FSBL application from the list. This creates an FSBL executable.

For more detailed information, see the SDK Help System.

Once you generate the FSBL, you must copy it into a standard location for the SDx environment flow.

Example:
samples/platforms/zc702_axis_io/sw/boot/fsbl.elf

For the SDx system compiler to use an FSBL, a BIF file must point to it, as defined by the sdx:bif attribute of the <sdx:image> element. Refer to the Software Platform XML Metadata Reference for more information on the sdx:bif attribute. The file must reside in the <path_to_platform>/sw/boot/ folder.

Tip: The BIF file for a Zynq AP SoC is very different from the BIF file for the Zynq UltraScale+ MPSoC device.
The following is an example boot.bif file for the Zynq®-7000 All Programmable (AP) SoC:
/* linux */
 the_ROM_image:
 {
   [bootloader]<boot/fsbl.elf>
   <bitstream> 
   <boot/u-boot.elf>
 }
The following is an example boot.bif file for the Zynq UltraScale+™ MPSoC device:
/* linux */
the_ROM_image:
{
  [fsbl_config] a53_x64
  [bootloader]<boot/fsbl.elf>
  [pmufw_image]<boot/pmufw.elf>
  [destination_device=pl] <bitstream>
  [destination_cpu=a53-0, exception_level=el-3, trustzone] <boot/bl31.elf>
  [destination_cpu=a53-0, exception_level=el-2] <boot/u-boot.elf>
}