Hardware Platform Creation


The hardware platform creation process consists of building a Vivado design and creating a Tcl script of SDSoC commands that captures the hardware interfaces supported, including clocks, interrupts, and bus interfaces. The SDSoC Platform Utility moves the Vivado project and associated files into the platform folder <path_to_platform>/hw/vivado.

This chapter assumes familiarity with the Vivado Design Suite and the ability to create a Vivado project for the hardware in your platform. It describes general requirements for the hardware in your platform, the Vivado project and the hardware platform folder.

Hardware Requirements

This section describes requirements on the hardware design component of an SDSoC platform. In general, nearly any design targeting the Zynq®-7000 All Programmable (AP) SoC or Zynq UltraScale+™ MPSoC device using the IP Integrator within the Vivado® Design Suite can be the basis for an SDSoC platform. The process of capturing the SDSoC hardware platform is conceptually straightforward.
  1. Build and verify the hardware system using the Vivado Design Suite and IP Integrator feature.
  2. Create a Tcl script that uses the SDSoC Vivado Tcl Commands.
  3. Specify the Vivado project and Tcl script in the SDSoC Platform Utility to build the platform.

There are several rules that the platform hardware design must observe.

  • The Vivado Design Suite project name must match the hardware platform name.
    Tip: If the Vivado design project contains more than one block diagram, the block diagram that has the same name as the hardware platform is the one that is used by the SDSoC Tcl script.
  • Every IP used in the platform design that is not part of the standard Vivado IP catalog must be local to the Vivado Design Suite project. References to external IP repository paths are not supported by the SDSoC Tcl script.
  • Every hardware platform design must contain a Processing System IP block from the Vivado IP catalog.
  • Every hardware port interface to the SDSoC platform must be an AXI, AXI4-Stream, clock, reset, or interrupt type interface only. Custom bus types or hardware interfaces must remain internal to the hardware platform.
  • Every platform must declare at least one general purpose AXI master port from the Processing System IP or an interconnect IP connected to such an AXI master port, that will be used by the SDSoC compilers for software control of datamover and accelerator IPs.
  • Every platform must declare at least one AXI slave port that will be used by the SDSoC compilers to access DDR from datamover and accelerator IPs.
  • To share an AXI port between the SDSoC environment and platform logic, for example S_AXI_ACP, you must export an unused AXI master or slave of an AXI Interconnect IP block connected to the corresponding AXI port, and the platform must use the ports with least significant indices.
  • Every platform AXI interface will be connected to a single data motion clock by the SDSoC environment.
    Tip: Accelerator functions generated by the SDSoC compilers might run on a different clock that is provided by the platform.
  • Every exported platform clock must have an accompanying Processor System Reset IP block from the Vivado IP catalog.
  • Platform interrupt inputs must be exported by a Concat (xlconcat) IP connected to the Processing System 7 IP IRQ_F2P port. IP blocks within a platform can use some of the sixteen available fabric interrupts, but must use the least significant bits of the IRQ_F2P port without gaps.