The Xilinx SDAccel™ Development Environment is part of the SDx™ Development Toolchain. This toolchain allows you to create FPGA accelerated designs using C/C++, OpenCL C, or RTL programming languages. You can create these designs in the SDx GUI environment or through a Makefile flow.

This tutorial walks you through the steps of building a basic OpenCL based design using the SDx GUI and learning some of the features that enable you to do performance profiling, and optimization.

Tutorial Design Description

This tutorial is based on the Xilinx SDAccel™ Github Examples, specifically the Vector Addition example. More information related to the Github examples can be found in SDAccel Environment Profiling and Optimization Guide.

Hardware and Software Requirements

Refer to the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing, (UG973) for a complete list and description of the system and software requirements for the Vivado® Design Suite.