Introduction

The Zynq®-7000 SoC and Zynq UltraScale+ MPSoC integrate the software programmability of an ARM®-based processor with the hardware programmability of an FPGA, enabling key analytics and hardware acceleration while integrating CPU, DSP, ASSP, and mixed-signal functionality on a single device. The SDSoC™ (software-defined system-on-chip) environment is a tool suite that includes an Eclipse-based integrated development environment (IDE) for implementing heterogeneous embedded systems using the Zynq-7000 SoC and Zynq UltraScale+ MPSoC platforms.

The SDSoC environment includes system compilers that transform C/C++ programs into complete hardware/software systems with select functions compiled into programmable logic to enable hardware acceleration of the selected functions. This guide provides software programmers with an appreciation of the underlying hardware used to provide the acceleration, including factors that might limit or improve performance, and a methodology to help achieve the highest system performance.

Although a detailed knowledge of hardware is not required for using SDSoC, an appreciation of the hardware resources available on the device and how a hardware function achieves very high performance through increased parallelism will help you select the appropriate compiler optimization directives to meet your performance needs.

The methodology can be summarized as follows:

  • Profile your software and identify functions that would benefit from hardware acceleration.

  • Optimize the data transfer between the CPU, often referred to as the Programmable System (PS), and the Programmable Logic (PL) fabric used to implement the hardware.

  • Optimize the parallelism of the hardware.

After providing an understanding of how hardware acceleration is achieved, this guide concludes with a number of real-world examples demonstrating the methodology and a performance checklist for use in your own SDSoC projects.