Xilinx SDK Predefined Design Flow

The predefined flow provided with Xilinx® SDK uses the fixed design, and comes with a fixed bitstream. In this design, there are five AXI Traffic Generators (ATGs), with one connected to each of the four High Performance ports (HP0-3) and one connected to the Accelerator Coherency Port (ACP). The ATGs are set up and controlled using one of the General Purpose (GP) ports. In addition, an AXI Performance Monitor (APM) is included in order to monitor the AXI traffic on the HP0-3 and ACP ports.

The Xilinx SDK predefined design flow includes the following steps:

  1. System Performance Modeling Using the SDK Predefined Design
  2. Configure FSBL Parameters