HLS Pragmas

Optimizations in Vivado HLS

In both SDAccel™ and SDSoC™ projects, the hardware kernel must be synthesized from the OpenCL™, C, or C++ language into RTL that can be implemented into the programmable logic of a Xilinx® device. Vivado® HLS synthesizes the RTL from the OpenCL, C, and C++ language descriptions.

Vivado HLS is intended to work with your SDAccel or SDSoC Development Environment project without interaction. However, Vivado HLS also provides pragmas that can be used to optimize the design: reduce latency, improve throughput performance, and reduce area and device resource utilization of the resulting RTL code. These pragmas can be added directly to the source code for the kernel.

IMPORTANT!:

Although the SDSoC environment supports the use of HLS pragmas, it does not support pragmas applied to any argument of the function interface (interface, array partition, or data_pack pragmas). Refer to "Optimizing the Hardware Function" in the SDSoC Environment Profiling and Optimization Guide (UG1235) for more information.