pragma HLS reset

Description

Adds or removes resets for specific state variables (global or static).

The reset port is used in an FPGA to restore the registers and block RAM connected to the reset port to an initial value any time the reset signal is applied. The presence and behavior of the RTL reset port is controlled using the config_rtl configuration file. The reset settings include the ability to set the polarity of the reset, and specify whether the reset is synchronous or asynchronous, but more importantly it controls, through the reset option, which registers are reset when the reset signal is applied. See Clock, Reset, and RTL Output in the Vivado Design Suite User Guide: High-Level Synthesis (UG902) for more information.

Greater control over reset is provided through the RESET pragma. If a variable is a static or global, the RESET pragma is used to explicitly add a reset, or the variable can be removed from the reset by turning off the pragma. This can be particularly useful when static or global arrays are present in the design.

Syntax

Place the pragma in the C source within the boundaries of the variable life cycle.

#pragma HLS reset variable=<a> off
Where:
  • variable=<a>: Specifies the variable to which the pragma is applied.
  • off: Indicates that reset is not generated for the specified variable.

Example 1

This example adds reset to the variable a in function foo even when the global reset setting is none or control:
void foo(int in[3], char a, char b, char c, int out[3]) {
#pragma HLS reset variable=a 

Example 2

Removes reset from variable a in function foo even when the global reset setting is state or all.

void foo(int in[3], char a, char b, char c, int out[3]) {
#pragma HLS reset variable=a off

See Also

Vivado Design Suite User Guide: High-Level Synthesis (UG902)