Command Line Flow

The System ILA debug core provides transaction level visibility into an accelerated kernel or function running on hardware. AXI traffic of interest can also be captured and viewed using the System ILA core.

The ILA core can be instantiated in the overall hardware of an existing RTL IP design, to enable debugging features within that design, or can be inserted automatically by the compiler. The XOCC compiler provides the --dk option to attach System ILA cores at the interfaces to the kernels for debugging and performance monitoring purposes.

The -–dk option to enable ILA IP core insertion has the following syntax:

 --dk <[chipscope|list_ports]<:compute_unit_name><:interface_name>>

In general, the <interface_name> is optional. If not specified, all ports are expected to be analyzed.

The chipscope option requires the explicit name of the compute unit to be provided for the <compute_unit_name> and <interface_name>.

The list_ports option generates a list of valid compute units and port combinations in the current design.


Multiple --dk option switches can be specified in a single command line to additively add interface monitoring capability.

Refer to the SDx Command and Utility Reference Guide for more information on any XOCC option.

Once the design is built, you can debug the design using the Hardware Manager as described in Vivado Design Suite User Guide: Programming and Debugging (UG908).