Hardware Component Requirements

The hardware design in the Vitis unified software platform should adhere to the following rules:

  • Every hardware platform design must contain a Processing System IP block from the IP catalog.

    Note:
    • Zynq® UltraScale+™ MPSoC and Zynq-7000 SoC devices are supported.
    • MicroBlaze processors are not supported for acceleration kernels, but can be part of the base hardware.
  • Every IP used in the platform design that is not part of the standard Vivado® IP catalog must be local to the Vivado Design Suite project. References to external IP repository paths are not supported by the write_hw_platform command.
  • Any external hardware port interface to the Vitis platform must be an AXI4, AXI4-Lite, AXI4-Stream, clock, reset type interface.

    Note:
    • Kernel-to-Kernel, Host-to-Kernel, and multiple PL memory controllers are supported.
    • HLS kernels have native AXI4-MM interfaces which must use contiguous memory.

      The XRT memory allocator provides contiguous buffers.

    • Custom bus-type or hardware interfaces must remain internal to the hardware design and cannot be declared for use by the v++ linker.
  • Every platform must declare at least one general-purpose AXI master port from the Processing System IP or an interconnect IP, connected to such an AXI master port. These are used for software control of accelerator IP.

    • sptags are supported for S_AXI interfaces that map memory. M_AXI_GP port sptags are not supported.
    Note: Explicit connection points for XRT kernel attachment are specified with the PFM.AXI_PORT sptag interface property and a matching --sp command argument to the v++ linker.
  • Streaming kernel interfaces are specified with the PFM.AXIS_PORT sptag interface property and a matching --sc command argument to the v++ linker.
  • Sharing an AXI port between the Vitis environment and platform logic, such as the S_AXI_HP0 port, is accomplished by attaching an AXI interconnect IP or AXI SmartConnect IP block to the interface. The platform logic must use the ports with the least significant indices on the interconnect with the remaining indices declared as enabled for use by the v++ linker.
  • Multiple clocks are supported. Every platform must provide and declar one or more clock nets sourced within the platform. The platform can have as many internal clocks as needed. These can, but are not required to, be declared for use by the v++ linker.
    • The PFM.CLOCK property is used to set clocking and associated reset information.
    • Your design must include a clock set as the default clock, with id=0 and status=fixed.
    • If available, a clock with id=1 and status=fixed will be used by the v++ linker to connect to the ap_clk2 port of an acceleration kernel.
    • Frequencies of either clock are unspecified, but the designer should consider device and timing constraints. Platforms can contain other clocks.
  • Every declared platform clock must have an accompanying Processor System Reset IP block from the Vivado IP catalog.
  • Platform interrupt inputs must use and declare an AXI interrupt controller (axi_intc) IP block connected to the Processing System. IP blocks within a platform can use some of the 16 available fabric interrupts.

    In the 2019.2 release, platform developers are responsible for wiring interrupts for use by XRT. Do not declare any PFM.IRQ properties. Future releases will automate the interrupt handling.

  • Memory access through the MIG controller must use the PFM.AXI_PORT property and specify the memport, sptag, and a memory field containing the memory instance name and address range.