Other Xilinx Utilities

Xilinx Software Command-Line Tool

Xilinx Software Command-line Tool (XSCT) is an interactive and scriptable command-line interface to the Vitis IDE. As with other Xilinx tools, the scripting language for XSCT is based on Tools Command Language (Tcl). You can run XSCT commands interactively or script the commands for automation. XSCT supports the following actions:
  • Create hardware, domains/board support packages (BSPs), and application projects
  • Manage repositories
  • Set toolchain preferences
  • Configure and build domains/BSPs and applications
  • Download and run applications on hardware targets
  • Create and flash boot images by running Bootgen and program_flash tools.

For more information about XSCT, refer to the Xilinx Software Command-Line Tool (XSCT) Reference Guide (UG1208).

Program FPGA

Program the FPGA with the bitstream.



The following table lists the options available on the Program FPGA dialog box:

Hardware Configuration
Specify the Bitstream and BMM files. These are provided by Vivado® Design Suite when you export your hardware design to the Vitis software platform.
Bitstream File
Specify the FPGA Bitstream.
BMM File
Specify the BMM file.
Software Configuration
Specify the program that is initialized at the reset start address for each processor in the Block RAM.
Processor
Name of the processor in the system.
ELF file
Specify the ELF file to initialize.
Program
Click this button to program the FPGA.

Dump/Restore Data File

The Vitis software platform allows you to copy the contents of a binary file to the target memory, or copy binary data from target memory to a file, through JTAG.

Launch Shell

Launch a command console window with Xilinx settings. This shell can be used for running XSDB, XSCT commands.

Import

In the Vitis IDE, you can also import projects that have previously been exported from the Vitis software platform.
  1. Go to File > Import > Vitis project exported zip file.

  2. Select the zip file exported from the Vitis software platform.

    Note: If projects with the same name exist in the current workspace, the project in the exported zip cannot be imported.

Export

Projects managed in the Vitis IDE can be exported to that you can move them around easily.

  1. Go to File > Export to open the Export Vitis Projects window.

  2. Select the system projects or platform projects you want to export.
  3. Set the export archive file name and destination directory. Selecting the Include build folders option includes build folders in the export zip file. This is generally not required because these files can be generated at the destination.
    Note: If any files are added to project by links, the referenced file will be added to the exported .zip file so that the project can be imported without referencing.

Generating Device Tree

The Vitis™ IDE can generate device trees. To generate a device tree, follow these steps:
  1. Select Xilinx > Repositories.
  2. Click New.
  3. Provide the local path for the device tree generato, which can be downloaded from GitHub.
  4. Select Xilinx > Generate Device Tree to open the Device Tree Generator.
  5. Provide the hardware specification file and the output directory (the output will be created here).

    You can change the settings for device tree blob (DTB) using the Modify Device Tree settings. The device tree path displays after successful generation.