Build Targets

The build target of the Vitis tool defines the nature and contents of the FPGA binary (.xclbin) created during compilation and linking. There are three different build targets: two emulation targets used for validation and debugging purposes: software emulation and hardware emulation, and the default system hardware target used to generate the FPGA binary (.xclbin) loaded into the Xilinx device.

Compiling for an emulation target is significantly faster than compiling for the real hardware. The emulation run is performed in a simulation environment, which offers enhanced debug visibility and does not require an actual accelerator card.

Table 1. Comparison of Emulation Flows with Hardware Execution
Software Emulation Hardware Emulation Hardware Execution
Host application runs with a C/C++ or OpenCL model of the kernels. Host application runs with a simulated RTL model of the kernels. Host application runs with actual hardware implementation of the kernels.
Used to confirm functional correctness of the system. Test the host / kernel integration, get performance estimates. Confirm that the system runs correctly and with desired performance.
Fastest build time supports quick design iterations. Best debug capabilities, moderate compilation time with increased visibility of the kernels. Final FPGA implementation, long build time with accurate (actual) performance results.

Software Emulation

The main goal of software emulation is to ensure functional correctness of the host program and kernels. For software emulation, both the host code and the kernel code are compiled to run on the host x86 processor. The v++ compiler does the minimum transformation of the kernel code to create the FPGA binary, in order to run the host program and kernel code together. The software emulation flow can be used for algorithm refinement, debugging functional issues, and letting developers iterate quickly through the code to make improvements. The programming model of development through fast compile and run iterations is preserved.

In the context of the Vitis unified software platform, software emulation on a CPU is the same as the iterative development process that is typical of CPU/GPU programming. In this type of development style, a programmer continuously compiles and runs an application as it is being developed.

TIP: For RTL kernels, software emulation can be supported if a C model is associated with the kernel. The RTL kernel wizard packaging step provides an option to associate C model files with the RTL kernel for support of software emulation flows.
As discussed in Vitis Compiler Command, the software emulation target is specified in the v++ command with the -t option:
v++ -t sw_emu ...

Hardware Emulation

The hardware emulation flow enables the programmer to check the functional correctness of the RTL description of the FPGA binary synthesized from the C, C++, or OpenCL kernel code.

Each kernel is compiled to a hardware model (RTL). During hardware emulation, kernels are run in the Vivado logic simulator, with a waveform viewer to examine the kernel design. In addition, hardware emulation provides performance and resource estimates for the hardware implementation.

In hardware emulation, compile and execution times are longer than for software emulation, but it provides a detailed, cycle-accurate, view of kernel activity. Xilinx recommends that you use small data sets for validation during hardware emulation to keep run times manageable.

IMPORTANT: The DDR memory model and the memory interface generator (MIG) model used in hardware emulation are high-level simulation models. These models provide good simulation performance, but only approximate latency values and are not cycle-accurate like the kernels. Therefore, performance numbers shown in the profile summary report are approximate, and should be used for guidance and for comparing relative performance between different kernel implementations.
As discussed in Vitis Compiler Command, the hardware emulation target is specified in the v++ command with the -t option:
v++ -t hw_emu ...

System Hardware Target

When the build target is the system hardware, v++ builds the FPGA binary for the Xilinx device by running synthesis and implementation on the design. Therefore, it is normal for this build target to take a longer period of time than generating either the software or hardware emulation targets in the Vitis IDE. However, the final FPGA binary can be loaded into the hardware of the accelerator card, or embedded processor platform, and the application can be run in its actual operating environment.

As discussed in Vitis Compiler Command, the system hardware target is specified in the v++ command with the -t option:
v++ -t hw ...