export_design

Description

Exports and packages the synthesized design as a compiled kernel object (.xo) for the Vitis application acceleration development flow, or as a packaged IP for Vivado Design Suite downstream tools.

Supported formats include:

  • Vivado IP catalog.
  • Synthesized or implemented design checkpoint (DCP) format.
  • Vitis application acceleration kernel (.xo).

The packaged project is written to the solution/impl folder of the active solution.

Syntax

export_design [OPTIONS]

Options

-description <string>

Provides a description for the catalog entry for the generated IP, used when packaging the IP.

-display_name <string>

Provides a display name for the catalog entry for the generated IP, used when packaging the IP.

-flow (syn | impl)

Obtains more accurate timing and usage data for the specified HDL using RTL synthesis. The option syn performs RTL synthesis. The option impl performs both RTL synthesis and implementation, including a detailed place and route of the synthesized gates. In the Vitis HLS GUI, these options appear as checkboxes labeled Vivado Synthesis and Vivado Synthesis, place and route stage, respectively.

-format (ip_catalog | xo | syn_dcp | sysgen)

Specifies the format to package the IP. The supported formats are:

  • ip_catalog: A format suitable for adding to the Xilinx IP catalog.
  • xo: A format accepted by the v++ compiler for linking in the Vitis application acceleration flow.
  • syn_dcp: Synthesized checkpoint file for Vivado Design Suite. If this option is used, RTL synthesis is automatically executed. Vivado implementation can be optionally added.
  • sysgen: Generate a Vivado IP and .zip archive for use in System Generator.
-ipname <string>
Provides the name component of the Vendor:Library:Name:Version (VLNV) identifier for generated IP.
-library <string>
Provides the library component of the Vendor:Library:Name:Version (VLNV) identifier for generated IP.
-output <string>
Specifies the output location of the generated IP, .xo, or DCP files. The file is written to the solution/impl folder of the current project if no output path is specified.
-rtl (verilog | VHDL)
Specifies which HDL is used when the -flow option is executed. If not specified, Verilog is the default language for the Vivado synthesized netlist.
-taxonomy <string>
Specifies the taxonomy for the catalog entry for the generated IP, used when packaging the IP.
-vendor <string>
Provides the vendor component of the Vendor:Library:Name:Version (VLNV) identifier for generated IP.
-version <string>
Provides the version component of the Vendor:Library:Name:Version (VLNV) identifier for generated IP.

Examples

Exports RTL for the Vitis application acceleration flow:

export_design -format xo

Exports the RTL as VHDL code in the Vivado IP catalog format. The VHDL is synthesized in Vivadosynthesis tool to obtain better timing and usage data:

export_design -rtl vhdl -format ip_catalog -flow syn