set_directive_bind_storage

Description

The set_directive_bind_storage command indicates that a specific storage type (type) is assigned to a variable (array, or function argument) in the RTL. If the directive is not specified, the Vitis HLS tool determines the storage type to assign. The HLS tool implements the specified storage type using specified implementations (-impl). The types are defined in the following table.

Table 1. Storage Types
Type Description
FIFO A FIFO. Vitis HLS determines how to implement this in the RTL, unless the -impl option is specified.
RAM_1P A single-port RAM. Vitis HLS determines how to implement this in the RTL, unless the -impl option is specified.
RAM_1WNR A RAM with 1 write port and N read ports, using N banks internally.
RAM_2P A dual-port RAM that allows read operations on one port and both read and write operations on the other port.
RAM_S2P A dual-port RAM that allows read operations on one port and write operations on the other port.
RAM_T2P A true dual-port RAM with support for both read and write on both ports.
ROM_1P A single-port ROM. Vitis HLS determines how to implement this in the RTL, unless the -impl option is specified.
ROM_2P A dual-port ROM.
ROM_NP A multi-port ROM.

For example, you can use the set_directive_bind_storage command to specify which type of memory, and which implementation to use for an array variable. This lets you control whether the array is implemented as a single or a dual-port RAM for example. This usage is important for arrays on the top-level function interface, because the memory type associated with the array determines the number and type of ports needed in the RTL, as discussed in Arrays on the Interface.

You can use the -latency option to specify the latency of the implementation. For block RAMs on the interface, the -latency option allows you to model off-chip, non-standard SRAMs at the interface, for example supporting an SRAM with a latency of 2 or 3. For internal operations, the -latency option allows the operation to be implemented using more pipelined stages. These additional pipeline stages can help resolve timing issues during RTL synthesis.

IMPORTANT: To use the -latency option, the operation must have an available multi-stage implementation. The HLS tool provides a multi-stage implementation for all basic arithmetic operations (add, subtract, multiply and divide), all floating-point operations, and all block RAMs.

For best results, Xilinx recommends that you use -std=c99 for C and -fno-builtin for C and C++. To specify the C compile options, such as -std=c99, use the Tcl command add_files with the -cflags option. Alternatively, select the Edit CFLAGs button in the Project Settings dialog box as described in Creating a New Vitis HLS Project.

Syntax

set_directive_bind_storage [OPTIONS] <location> <variable> <type>
  • <location> is the location (in the format function[/label]) which contains the variable.
  • <variable> is the variable to be assigned.
  • <type> indicates the storage type to assign to the specified variable.

    Supported types include: fifo, ram_1p, ram_1wnr, ram_2p, ram_s2p, ram_t2p, rom_1p, rom_2p, rom_np.

Options

-impl <value>

Defines the implementation for the specified storage type (type). Supported implementations include: bram, lutram, uram, srl.

-latency <int>

Defines the default latency for the binding of the storage type to the implementation. The valid latency varies according to the specified type and impl. The default is -1, which lets Vitis HLS choose the latency.

Example 1

In the following example, the <coeffs[128]> variable is an argument to the top-level function foo_top. The directive specifies that coeffs uses a single port RAM implemented on a BRAM core from the library.

set_directive_bind_storage -impl bram "foo_top" coeffs RAM_1P
TIP: The ports created in the RTL to access the values of coeffs are defined in the RAM_1P core.

See Also