Sometimes a C-based specification is written with a sequence of operations, resulting in a long chain of operations in RTL. With a small clock period, this can increase the latency in the design. By default, the Vitis HLS tool rearranges the operations using associative and commutative properties. This rearrangement creates a balanced tree that can shorten the chain, potentially reducing latency in the design at the cost of extra hardware.

The set_directive_expression_balance command allows this expression balancing to be turned off, or on, within a specified scope.


set_directive_expression_balance [OPTIONS] <location>
  • <location> is the location (in the format function[/label]) where expression balancing should be disabled, or enabled.



Turns off expression balancing at the specified location.

TIP: Removing the -off option from the directive enables expression balancing, which is the default mode. This can be used to disable the directive without removing it from your code.


Disables expression balancing within function My_Func.

set_directive_expression_balance -off My_Func

Explicitly enables expression balancing in function My_Func2.

set_directive_expression_balance My_Func2

See Also