Analyzing the Results of Synthesis

After synthesis completes, Vitis HLS automatically creates synthesis reports to help you understand the performance of the implementation. Examples of these reports include the Synthesis Summary report, Schedule Viewer, and Dataflow Viewer. You can view these reports from the Analysis perspective in the Vitis HLS IDE.

Open the Analysis perspective by clicking Analysis in the upper right corner of the Vitis HLS IDE. The Analysis perspective is provided as a place to view different elements of your project to evaluate the results of synthesis and the performance of your current solution.

By default, the Analysis perspective opens with the Schedule Viewer displayed. As shown in the following figure the Analysis perspective includes multiple windows and views:

Schedule Viewer
Shows each operation and control step of the function, and the clock cycle that it executes in.
Module Hierarchy
Shows the function hierarchy and the performance characteristics of the current hierarchy.
Performance Profile
Shows the Loops from the top-level function without any performance information.
Resource Profile
Shows the resource usage of different elements of the synthesized function.
Properties view
Shows the properties of the currently selected control step or operation in the Schedule Viewer.
Figure 1: Analysis Perspective

The Module Hierarchy view provides an overview of the entire RTL design. You can use this view to quickly navigate the hierarchy of the RTL design.

  • The Module Hierarchy view shows the resources and latency contribution for each block in the RTL hierarchy.
  • The Module Hierarchy indicates directly any II or timing violation. In case of timing violations, the hierarchy window will also show the total negative slack observed in a specific module.

The Performance Profile view provides details on the performance of the block currently selected in the Module Hierarchy view.

  • Performance is measured in terms of latency and the initiation interval.
  • This view also includes details on whether the block was pipelined or not.

The Resource Profile view shows the resources used at the selected level of hierarchy, and shows the control state of the operations used.

Schedule Viewer

The Schedule Viewer provides a detailed view of the synthesized RTL, showing each operation and control step of the function, and the clock cycle that it executes in. It helps you to identify any loop dependencies that are preventing parallelism, timing violations, and data dependencies.

The Schedule Viewer is displayed by default in the Analysis perspective. You can open it from the Module Hierarchy window by right-clicking a module and selecting Open Schedule Viewer from the menu.

In the Schedule Viewer,

  • The left vertical axis shows the names of operations and loops in the RTL hierarchy. Operations are in topological order, implying that an operation on line n can only be driven by operations from a previous line, and will only drive an operation in a later line.
  • The top horizontal axis shows the clock cycles in consecutive order.
  • The vertical dashed line in each clock cycle shows the reserved portion of the clock period due to clock uncertainty. This time is left by the tool for the Vivado back-end processes, like place and route.
  • Each operation is shown as a gray box in the table. The box is horizontally sized according to the delay of the operation as percentage of the total clock cycle. In case of function calls, the provided cycle information is equivalent to the operation latency.
  • Multi-cycle operations are shown as gray boxes with a horizontal line through the center of the box.
  • The Schedule Viewer also displays general operator data dependencies as solid blue lines. As shown in the figure below, when selecting an operation you can see solid blue arrows highlighting the specific operator dependencies. This gives you the ability to perform detailed analysis of data dependencies. The green dotted line indicates an inter-iteration data dependency.
  • Memory dependencies are displayed using golden lines.
  • In addition, lines of source code are associated with each operation in the Schedule Viewer report. Right-click the operation to use the Goto Source command to open the input source code associated with the operation.

In the figure below, the loop called RD_Loop_Row is selected. This is a pipelined loop and the initiation interval (II) is explicitly stated in the loop bar. Any pipelined loop is visualized unfolded, meaning one full iteration is shown in the schedule viewer. Overlap, as defined by II, is marked by a thick clock boundary on the loop marker.

The total latency of a single iteration is equivalent to the number of cycles covered by the loop marker. In this case, it is three cycles.

Figure 2: Schedule Viewer

The Schedule Viewer displays a menu bar at the top right of the report that includes the following features:

  • A drop-down menu, initially labeled Focus Off, that lets you specify operations or events in the report to select.
  • A text search field to search for specific operations or steps (), and commands to Scroll Up or Scroll Down through the list of objects that match your search text
  • Zoom In, Zoom Out, and Zoom Fit commands ().
  • The Filter command () lets you dynamically filter the operations that are displayed in the viewer. You can filter operations by type, or by clustered operations.
    • Filtering by type allows you to limit what operations get presented based on their functionality. For example, visualizing only adders, multipliers, and function calls will remove all of the small operations such as “and” and “or”s.
    • Filtering by clusters exploits the fact that the scheduler is able to group basic operations and then schedule them as one component. The cluster filter setting can be enabled to color the clusters or even collapse them into one large operation in the viewer. This allows a more concise view of the schedule.
Figure 3: Operation Causing Violation

You can quickly locate II violations using the drop-down menu in the Schedule Viewer, as shown in the figure above. You can also select it through the context menu in the Module Hierarchy view.

To locate the operations causing the violation in the source code, right-click the operation and use the Goto Source command, or double-click the operation and the source viewer will appear and identify the root of the object in the source.

Timing violations can also be quickly found from the Module Hierarchy view context menu, or by using the drop-down menu in the Schedule Viewer menu. A timing violation is a path of operations requiring more time than the available clock cycle. To visualize this, the problematic operation is represented in the Schedule Viewer in a red box.

By default all dependencies (blue lines) are shown between each operation in the critical timing path.

Properties View

At the bottom of the Schedule Viewer, as shown in the top figure, is the Properties view that displays the properties of a currently selected object in the Schedule Viewer. This lets you see details of the specific function, loop, or operation that is selected in the Schedule Viewer. The types of elements that can be selected, and the properties displayed include:

  • Functions or Loops
    Initiation Interval (II)
    The number of clock cycles before the function or loop can accept new input data.
    Loop Iteration Latency
    The number of clock cycles it takes to complete one iteration of the loop.
    The number of clock cycles required for the function to compute all output values, or for the loop to complete all iterations.
    Indicates that the function or loop are pipelined in the RTL design.
    The timing slack for the function or loop.
    The number of iterations a loop completes.
    Resource Utilization
    Displays the number of BRAM, DSP, LUT, or FF used to implement the function or loop.
  • Operation and Storage Mapping
    Location which contains the code.
    Op Code
    Operation which has been scheduled, for example, add, sub, and mult. For more information, refer to the BIND_OP or BIND_STORAGE pragmas or directives.
    Op Latency
    Displays the default or specified latency for the binding of the operation or storage.
    Bitwidth of the Operation.
    Defines the implementation used for the specified operation or storage.

Dataflow Viewer

The DATAFLOW optimization is a dynamic optimization which can only be fully understood after the RTL co-simulation is complete. Due to this fact, the Dataflow viewer lets you see the dataflow structure inferred by the tool, inspect the channels (FIFO/PIPO), and examine the effect of channel depth on performance. Performance data is back-annotated to the Dataflow viewer from the co-simulation results.
IMPORTANT: You can open the Dataflow viewer without running RTL co-simulation, but your view will not contain important performance information such as read/write block times, co-sim depth, and stall times.

You must apply the DATAFLOW pragma or directive to your design for the Dataflow viewer to be populated. You can apply dataflow to the top-level function, or specify regions of a function, or loops. The Dataflow viewer displays a representation of the dataflow graph structure, showing the different processes and the underlying producer-consumer connections.

In the Module Hierarchy view, the icon beside the function indicates that a Dataflow Viewer report is available. When you see this icon, you can right-click the function and use the Open Dataflow Viewer command.

Figure 4: Dataflow Viewer

Features of the Dataflow viewer include the following:

  • Source Code browser.
  • Automatic cross-probing from process/channel to source code.
  • Filtering of ports and channel types.
  • Process and Channel table details the characteristics of the design:
    • Channel Profiling (FIFO sizes etc), enabled from Solution Settings dialog box.
    • Process Read Blocking/Write Blocking/Stalling Time reported after RTL co-simulation.
      IMPORTANT: You must use cosim_design -enable_dataflow_profiling to capture data for the Dataflow viewer, and your test bench must run at least two iterations of the top-level function.
    • Process Latency and II displayed.
    • Channel type and widths are displayed in the Channel table.
    • Automatic cross-probing from Process and Channel table to the Graph and Source browser.
    • Hover over channel or process to display tooltips with design information.

The Dataflow viewer can help with performance debugging your designs. When your design deadlocks during RTL co-simulation, the GUI will open the Dataflow viewer and highlight the channels and processes involved in the deadlock so you can determine if the cause is insufficient FIFO depth, for instance.

When your design does not perform as expected, the Process and Channels table can help you understand why. A process can stall waiting to read input, or can stall because it cannot write output. The channel table provides you with stalling percentages, as well as identifying if the process is "read blocked" or "write blocked."

TIP: If you use a Tcl script to create the Vitis HLS project, you can still open it in the GUI to analyze the design.