rst

Target Reset.

Syntax

rst [options]

Reset the active target.

Options

Option Description
-processor Reset the active processor target.
-cores Reset the active processor group. This reset type is supported only on Zynq, ZynqMP, and Versal devices. A processor group is defined as a set of processor cores and on-chip peripherals like OCM.
-system Reset the active System. The is the default reset.
-srst Generate system reset for active target. With JTAG this is done by generating a pulse on the SRST pin on the JTAG cable assocated with the active target.
-por Generate power on reset for active target. With JTAG this is done by generating a pulse on the POR pin on the JTAG cable assocated with the active target.
-ps Generate PS only reset on Zynq MP. This is supported only through MicroBlaze PMU target.
-stop Suspend cores after reset. If this option is not specified, debugger choses the default action, which is to resume the cores for -system, and suspend the cores for -processor, and -cores. This option is only supported with -processor, -cores, and -system options.
-start Resume the cores after reset. See description of -stop option for more details.
-endianness <value> Set the data endianness to <value>. The following values are supported. le - Little endian be - Big endian This option is supported with APU, RPU, A9, A53, and A72 targets. If this option is not specified, the current configuration is not changed.
-code-endianness <value> Set the instruction endianness to <value>. The following values are supported. le - Little endian be - Big endian This option is supported with APU, RPU, A9, A53, and A72 targets. If this option is not specified, the current configuration is not changed.
-isa <isa-name> Set ISA to <isa-name>. Supported isa-names are ARM/A32, A64, and Thumb. This option is supported with APU, RPU, A9, A53, and A72 targets. If this option is not specified, the current configuration is not changed.
-clear-registers Clear CPU registers after a reset is triggered. This option is useful while triggerring a reset after the device is powered up. Otherwise, debugger can end up reading invalid system addresses based on the register contents. Clearing the registers will avoid unpredictable behavior. This option is supported for ARM targets, when used with -processor
-cores.
-type <reset type> The following reset types are supported. pmc-por, pmc-srst, ps-por, ps-srst, pl-por and pl-srst This option is supported only for Versal devices.

Note(s)

  • For Versal devices, default subsystem is activated thru IPI channel 5, before triggering the processor reset. This is needed since PLM doesn't activate the subsystem when PS elfs are not part of the PDI. If IPI channel is not enabled in Vivado design, subsystem cannot be activated. This will cause runtime issues if PM API are used.

Returns

Nothing, if reset if successful. Error string, if reset is unsupported.