Resource Utilization for AXI UART16550 v2.0

Vivado Design Suite Release 2022.1

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Kintex-7

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
C_HAS_EXTERNAL_RCLK
C_HAS_EXTERNAL_XIN
C_IS_A_16550
C_S_AXI_ACLK_FREQ_HZ_d
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xc7k480t ffg901 3 uart_16550_1 1 1 16550 300 s_axi_aclk=300 355 319 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 3 uart_16550_2 0 0 16550 200 s_axi_aclk=200 354 308 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 3 uart_16550_3 0 0 16450 200 s_axi_aclk=200 243 261 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 3 uart_16550_4 1 1 16450 300 s_axi_aclk=300 252 271 0 0 0 PRODUCTION 1.12 2017-02-17

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