Performance and Resource Utilization for Embedded Memory Generator v1.0

Vivado Design Suite Release 2019.2

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
Maximum frequency is determined for one clock input, while other clock inputs have fixed frequencies. The fixed clocks and their frequencies are stated for each test case.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2019.2 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Data is provided for the following device families:

versal
zynquplus

versal

Part Information			Configuration Parameters																												Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	XPM_SELECT	MEMORY_TYPE	MEMORY_SIZE	MEMORY_PRIMITIVE	CLOCKING_MODE	ECC_MODE	MEMORY_INIT_FILE	WAKEUP_TIME	MESSAGE_CONTROL	VERSION	WRITE_DATA_WIDTH_A	READ_DATA_WIDTH_A	ENABLE_BYTE_WRITES_A	BYTE_WRITE_WIDTH_A	ADDR_WIDTH_A	READ_RESET_VALUE_A	READ_LATENCY_A	WRITE_MODE_A	WRITE_DATA_WIDTH_B	READ_DATA_WIDTH_B	ENABLE_BYTE_WRITES_B	BYTE_WRITE_WIDTH_B	ADDR_WIDTH_B	READ_RESET_VALUE_B	READ_LATENCY_B	WRITE_MODE_B	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvc1902	vsva2197	1LP	xpm_mem_bram_sdp_ic_versal_1LP	2	Simple_Dual_Port_RAM	7684096	BRAM	Independent_Clock	No_ECC	none	Disable_Sleep	1	0	938	938	false	8	27	0	2	READ_FIRST	938	938	false	8	22	7fe5a72a67b8d9540112155c7205fe33b5b1640de9532dc415791c136065643057e23d05f255355934f1627bd2aaa510ad6219be8ee7ccb48b727eed87ee0a4fc537c261e3373f7798d5b2f79e4feafb2df42912b8441afdb696f5535671b3c05a5201a087c87dbc8c76918af2a20d713d6807cc6f	15	READ_FIRST	clkb=100	clka	610	5	12207	0	210	0	ENGINEERING-SAMPLE 1.02.09 07-10-2019

zynquplus

Part Information			Configuration Parameters																												Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	XPM_SELECT	MEMORY_TYPE	MEMORY_SIZE	MEMORY_PRIMITIVE	CLOCKING_MODE	ECC_MODE	MEMORY_INIT_FILE	WAKEUP_TIME	MESSAGE_CONTROL	VERSION	WRITE_DATA_WIDTH_A	READ_DATA_WIDTH_A	ENABLE_BYTE_WRITES_A	BYTE_WRITE_WIDTH_A	ADDR_WIDTH_A	READ_RESET_VALUE_A	READ_LATENCY_A	WRITE_MODE_A	WRITE_DATA_WIDTH_B	READ_DATA_WIDTH_B	ENABLE_BYTE_WRITES_B	BYTE_WRITE_WIDTH_B	ADDR_WIDTH_B	READ_RESET_VALUE_B	READ_LATENCY_B	WRITE_MODE_B	Fixed clocks (MHz)	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xczu9eg	ffvb1156	-1LV	xpm_mem_bram_sdp_ic_vup_1LV	2	Simple_Dual_Port_RAM	7684096	BRAM	Independent_Clock	No_ECC	none	Disable_Sleep	1	0	938	938	false	8	27	0	2	READ_FIRST	938	938	false	8	22	7fe5a72a67b8d9540112155c7205fe33b5b1640de9532dc415791c136065643057e23d05f255355934f1627bd2aaa510ad6219be8ee7ccb48b727eed87ee0a4fc537c261e3373f7798d5b2f79e4feafb2df42912b8441afdb696f5535671b3c05a5201a087c87dbc8c76918af2a20d713d6807cc6f	15	READ_FIRST	clkb=100	clka	516	56	12207	0	208	1	PRODUCTION 1.25 06-14-2019

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