Resource Utilization for Queue DMA Subsystem for PCI Express v4.0

Vivado Design Suite Release 2021.1

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Versal ACAP

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
functional_mode
device_port_type
pcie_blk_locn
pl_link_cap_max_link_width
pl_link_cap_max_link_speed
pipe_sim
axist_bypass_en
xdma_axilite_slave
dsc_byp_mode
cfg_ext_if
tl_pf_enable_reg
pipe_line_stage
SRIOV_CAP_ENABLE
acs_ext_cap_enable
pf0_bar4_enabled_qdma
PF0_SRIOV_CAP_INITIAL_VF
PF1_SRIOV_CAP_INITIAL_VF
PF2_SRIOV_CAP_INITIAL_VF
PF3_SRIOV_CAP_INITIAL_VF
dma_intf_sel_qdma
en_bridge_slv
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvc1902 vsva2197 3HP G3x16_mm_st_4PF_252VF_SRIOV_BRIDGE_BYPASS_ACS_CFG_EXT_versal_bep AXI_Bridge X1Y2 X16 8.0_GT/s true true true Descriptor_bypass_and_internal 4 0 true true true 60 60 60 72 AXI_MM_and_AXI_Stream_with_Completion true user_clk_sd=250 33558 26109 0 43 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x16_mm_st_4PF_252VF_SRIOV_BRIDGE_BYPASS_ACS_CFG_EXT_versal_brp AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1Y2 X16 8.0_GT/s true true true Descriptor_bypass_and_internal 2 0 true true true 60 60 AXI_MM_and_AXI_Stream_with_Completion true user_clk_sd=250 34108 25226 0 35 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x16_mm_st_4PF_252VF_SRIOV_BRIDGE_BYPASS_ACS_CFG_EXT_versal_qdma X1Y2 X16 8.0_GT/s true true true Descriptor_bypass_and_internal 4 0 true true true 60 60 60 72 AXI_MM_and_AXI_Stream_with_Completion true user_clk_sd=250 97863 86302 0 107 19 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x16_mm_st_4PF_252VF_SRIOV_BRIDGE_versal_bep AXI_Bridge X1Y2 X16 8.0_GT/s true true 4 0 true true 64 60 60 68 AXI_MM_and_AXI_Stream_with_Completion true user_clk_sd=250 33563 26101 0 43 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x16_mm_st_4PF_252VF_SRIOV_BRIDGE_versal_brp AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1Y2 X16 8.0_GT/s true true 2 0 true true 64 60 AXI_MM_and_AXI_Stream_with_Completion true user_clk_sd=250 34093 25225 0 35 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x16_mm_st_4PF_252VF_SRIOV_BRIDGE_versal_qdma X1Y2 X16 8.0_GT/s true true 4 0 true true 64 60 60 68 AXI_MM_and_AXI_Stream_with_Completion true user_clk_sd=250 96425 85358 0 107 19 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x16_mm_st_versal_bep AXI_Bridge X1Y2 X16 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_MM_and_AXI_Stream_with_Completion user_clk_sd=250 33565 26101 0 43 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x16_mm_st_versal_brp AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1Y2 X16 8.0_GT/s Descriptor_bypass_and_internal 2 0 true true 64 60 AXI_MM_and_AXI_Stream_with_Completion user_clk_sd=250 34110 25225 0 35 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x16_mm_st_versal_qdma X1Y2 X16 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_MM_and_AXI_Stream_with_Completion user_clk_sd=250 89726 78880 0 89 19 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x16_mm_versal_bep AXI_Bridge X1Y2 X16 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_MM user_clk_sd=250 33588 26101 0 43 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x16_mm_versal_brp AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1Y2 X16 8.0_GT/s Descriptor_bypass_and_internal 2 0 true true 64 60 AXI_MM user_clk_sd=250 34105 25225 0 35 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x16_mm_versal_qdma X1Y2 X16 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_MM user_clk_sd=250 64425 55898 0 68 14 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x16_st_versal_bep AXI_Bridge X1Y2 X16 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_Stream_with_Completion user_clk_sd=250 33565 26101 0 43 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x16_st_versal_brp AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1Y2 X16 8.0_GT/s Descriptor_bypass_and_internal 2 0 true true 64 60 AXI_Stream_with_Completion user_clk_sd=250 34103 25225 0 35 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x16_st_versal_qdma X1Y2 X16 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_Stream_with_Completion user_clk_sd=250 75700 62064 0 65 18 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x1_mm_st_versal_bep AXI_Bridge X1Y2 X1 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_MM_and_AXI_Stream_with_Completion user_clk_sd=250 15287 15062 0 15 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x1_mm_st_versal_brp AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1Y2 X1 8.0_GT/s Descriptor_bypass_and_internal 2 0 true true 64 60 AXI_MM_and_AXI_Stream_with_Completion user_clk_sd=250 14369 13710 0 7 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x1_mm_st_versal_qdma X1Y2 X1 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_MM_and_AXI_Stream_with_Completion user_clk_sd=250 56736 58340 0 28 18 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x1_mm_versal_bep AXI_Bridge X1Y2 X1 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_MM user_clk_sd=250 15287 15062 0 15 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x1_mm_versal_brp AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1Y2 X1 8.0_GT/s Descriptor_bypass_and_internal 2 0 true true 64 60 AXI_MM user_clk_sd=250 14371 13710 0 7 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x1_mm_versal_qdma X1Y2 X1 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_MM user_clk_sd=250 36799 38353 0 21 13 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x1_st_versal_bep AXI_Bridge X1Y2 X1 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_Stream_with_Completion user_clk_sd=250 15268 15062 0 15 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x1_st_versal_brp AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1Y2 X1 8.0_GT/s Descriptor_bypass_and_internal 2 0 true true 64 60 AXI_Stream_with_Completion user_clk_sd=250 14369 13710 0 7 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x1_st_versal_qdma X1Y2 X1 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_Stream_with_Completion user_clk_sd=250 47317 47037 0 24 17 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x4_mm_st_versal_bep AXI_Bridge X1Y2 X4 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_MM_and_AXI_Stream_with_Completion user_clk_sd=250 16924 16376 0 19 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x4_mm_st_versal_brp AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1Y2 X4 8.0_GT/s Descriptor_bypass_and_internal 2 0 true true 64 60 AXI_MM_and_AXI_Stream_with_Completion user_clk_sd=250 16102 15027 0 11 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x4_mm_st_versal_qdma X1Y2 X4 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_MM_and_AXI_Stream_with_Completion user_clk_sd=250 60170 61033 0 37 18 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x4_mm_versal_bep AXI_Bridge X1Y2 X4 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_MM user_clk_sd=250 16924 16376 0 19 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x4_mm_versal_brp AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1Y2 X4 8.0_GT/s Descriptor_bypass_and_internal 2 0 true true 64 60 AXI_MM user_clk_sd=250 16102 15027 0 11 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x4_mm_versal_qdma X1Y2 X4 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_MM user_clk_sd=250 39502 40565 0 28 13 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x4_st_versal_bep AXI_Bridge X1Y2 X4 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_Stream_with_Completion user_clk_sd=250 16921 16376 0 19 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x4_st_versal_brp AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1Y2 X4 8.0_GT/s Descriptor_bypass_and_internal 2 0 true true 64 60 AXI_Stream_with_Completion user_clk_sd=250 16116 15027 0 11 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x4_st_versal_qdma X1Y2 X4 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_Stream_with_Completion user_clk_sd=250 50196 48909 0 30 17 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x8_mm_st_versal_bep AXI_Bridge X1Y2 X8 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_MM_and_AXI_Stream_with_Completion user_clk_sd=250 20977 19046 0 27 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x8_mm_st_versal_brp AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1Y2 X8 8.0_GT/s Descriptor_bypass_and_internal 2 0 true true 64 60 AXI_MM_and_AXI_Stream_with_Completion user_clk_sd=250 20518 17854 0 19 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x8_mm_st_versal_qdma X1Y2 X8 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_MM_and_AXI_Stream_with_Completion user_clk_sd=250 67797 66400 0 55 18 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x8_mm_versal_bep AXI_Bridge X1Y2 X8 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_MM user_clk_sd=250 20977 19046 0 27 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x8_mm_versal_brp AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1Y2 X8 8.0_GT/s Descriptor_bypass_and_internal 2 0 true true 64 60 AXI_MM user_clk_sd=250 20533 17854 0 19 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x8_mm_versal_qdma X1Y2 X8 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_MM user_clk_sd=250 45563 44918 0 42 13 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x8_st_versal_bep AXI_Bridge X1Y2 X8 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_Stream_with_Completion user_clk_sd=250 20977 19046 0 27 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x8_st_versal_brp AXI_Bridge Root_Port_of_PCI_Express_Root_Complex X1Y2 X8 8.0_GT/s Descriptor_bypass_and_internal 2 0 true true 64 60 AXI_Stream_with_Completion user_clk_sd=250 20533 17854 0 19 5 ENGINEERING-SAMPLE 1.04 06-25-2020
xcvc1902 vsva2197 3HP G3x8_st_versal_qdma X1Y2 X8 8.0_GT/s Descriptor_bypass_and_internal 4 0 true true 64 60 60 68 AXI_Stream_with_Completion user_clk_sd=250 55492 52692 0 42 17 ENGINEERING-SAMPLE 1.04 06-25-2020

Virtex UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
functional_mode
device_port_type
pcie_blk_locn
pl_link_cap_max_link_width
pl_link_cap_max_link_speed
pipe_sim
axist_bypass_en
xdma_axilite_slave
dsc_byp_mode
cfg_ext_if
tl_pf_enable_reg
pipe_line_stage
SRIOV_CAP_ENABLE
acs_ext_cap_enable
pf0_bar4_enabled_qdma
PF0_SRIOV_CAP_INITIAL_VF
PF1_SRIOV_CAP_INITIAL_VF
PF2_SRIOV_CAP_INITIAL_VF
PF3_SRIOV_CAP_INITIAL_VF
dma_intf_sel_qdma
en_bridge_slv
Fixed clocks (MHz) LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu9p flgb2104 -3 G3x16_mm X1Y2 X16 8.0_GT/s Descriptor_bypass_and_internal 4 true true 64 60 60 68 AXI_MM DUT/inst/pcie4_ip_i/inst/my_ip_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[32].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/my_ip_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=400 sys_clk=100 sys_clk_gt=100 73840 76792 0 90 14 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -3 G3x16_mm_st X1Y2 X16 8.0_GT/s Descriptor_bypass_and_internal 4 true true 64 60 60 68 AXI_MM_and_AXI_Stream_with_Completion DUT/inst/pcie4_ip_i/inst/my_ip_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[32].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/my_ip_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=400 sys_clk=100 sys_clk_gt=100 98743 99882 0 111 19 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -3 G3x16_mm_st_4PF_252VF_SRIOV_BRIDGE X1Y2 X16 8.0_GT/s true true 4 true true 64 60 60 68 AXI_MM_and_AXI_Stream_with_Completion true DUT/inst/pcie4_ip_i/inst/my_ip_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[32].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/my_ip_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=400 sys_clk=100 sys_clk_gt=100 105166 106354 0 129 19 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -2 G3x16_mm_st_4PF_252VF_SRIOV_BRIDGE_BYPASS_ACS_CFG_EXT X1Y2 X16 8.0_GT/s true true true Descriptor_bypass_and_internal true 4 true true true 60 60 60 72 AXI_MM_and_AXI_Stream_with_Completion true DUT/inst/pcie4_ip_i/inst/my_ip_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[32].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/my_ip_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=400 sys_clk=100 sys_clk_gt=100 106396 107641 0 129 19 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -3 G3x16_st X1Y2 X16 8.0_GT/s Descriptor_bypass_and_internal 4 true true 64 60 60 68 AXI_Stream_with_Completion DUT/inst/pcie4_ip_i/inst/my_ip_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[32].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/my_ip_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[15].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=400 sys_clk=100 sys_clk_gt=100 85318 83079 0 87 18 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -3 G3x1_mm X1Y2 X1 8.0_GT/s Descriptor_bypass_and_internal 4 true true 64 60 60 68 AXI_MM DUT/inst/pcie4_ip_i/inst/my_ip_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=400 axi_aclk=62 sys_clk=100 sys_clk_gt=100 39268 42921 0 43 13 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -3 G3x1_mm_st X1Y2 X1 8.0_GT/s Descriptor_bypass_and_internal 4 true true 64 60 60 68 AXI_MM_and_AXI_Stream_with_Completion DUT/inst/pcie4_ip_i/inst/my_ip_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=400 axi_aclk=62 sys_clk=100 sys_clk_gt=100 58715 63010 0 50 18 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -3 G3x1_st X1Y2 X1 8.0_GT/s Descriptor_bypass_and_internal 4 true true 64 60 60 68 AXI_Stream_with_Completion DUT/inst/pcie4_ip_i/inst/my_ip_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[0].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=400 axi_aclk=62 sys_clk=100 sys_clk_gt=100 50044 51731 0 46 17 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -3 G3x4_mm X1Y2 X4 8.0_GT/s Descriptor_bypass_and_internal 4 true true 64 60 60 68 AXI_MM DUT/inst/pcie4_ip_i/inst/my_ip_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=400 axi_aclk=125 sys_clk=100 sys_clk_gt=100 41885 46094 0 50 13 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -3 G3x4_mm_st X1Y2 X4 8.0_GT/s Descriptor_bypass_and_internal 4 true true 64 60 60 68 AXI_MM_and_AXI_Stream_with_Completion DUT/inst/pcie4_ip_i/inst/my_ip_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=400 axi_aclk=125 sys_clk=100 sys_clk_gt=100 61881 66680 0 59 18 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -3 G3x4_st X1Y2 X4 8.0_GT/s Descriptor_bypass_and_internal 4 true true 64 60 60 68 AXI_Stream_with_Completion DUT/inst/pcie4_ip_i/inst/my_ip_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[3].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=400 axi_aclk=125 sys_clk=100 sys_clk_gt=100 52653 54581 0 52 17 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -3 G3x8_mm X1Y2 X8 8.0_GT/s Descriptor_bypass_and_internal 4 true true 64 60 60 68 AXI_MM DUT/inst/pcie4_ip_i/inst/my_ip_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[32].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/my_ip_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=400 sys_clk=100 sys_clk_gt=100 48471 51914 0 64 13 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -3 G3x8_mm_st X1Y2 X8 8.0_GT/s Descriptor_bypass_and_internal 4 true true 64 60 60 68 AXI_MM_and_AXI_Stream_with_Completion DUT/inst/pcie4_ip_i/inst/my_ip_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[32].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/my_ip_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=400 sys_clk=100 sys_clk_gt=100 70096 73514 0 77 18 PRODUCTION 1.27 02-28-2020
xcvu9p flgb2104 -3 G3x8_st X1Y2 X8 8.0_GT/s Descriptor_bypass_and_internal 4 true true 64 60 60 68 AXI_Stream_with_Completion DUT/inst/pcie4_ip_i/inst/my_ip_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[32].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[3].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK=500 DUT/inst/pcie4_ip_i/inst/my_ip_pcie4_ip_gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/my_ip_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.my_ip_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_cpll_cal_gtye4.gen_cpll_cal_inst[7].gen_inst_cpll_cal.gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_inst/gtwizard_ultrascale_v1_7_9_gtye4_cpll_cal_tx_i/bufg_gt_txoutclkmon_inst/O=400 sys_clk=100 sys_clk_gt=100 59487 59816 0 64 17 PRODUCTION 1.27 02-28-2020

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