Performance and Resource Utilization for Soft ECC Proxy v1.0

Vivado Design Suite Release 2023.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Resource figures are taken from the utilization report issued at the end of implementation using the Out-of-Context flow in Vivado Design Suite.
The Out-of-Context IP constraints include HD.CLK_SRC properties as required to ensure correct hold timing closure: these properties are enabled using the Tcl command: set_param ips.includeClockLocationConstraints true
Maximum frequency is measured using the Out-of-Context flow to synthesize and implement the IP instance in isolation. This ensures that the design is not distorted in order to route to device pins.
Maximum frequency is the result of a binary search of attempted clock period constraints. The reported figure is the highest frequency at which the design met timing.
LUT figures do not include LUTs used as pack-thrus, but do include LUTs used as memory.
Default Vivado Design Suite 2023.1 settings were used. You may be able to improve on these figures using different settings. Because surrounding circuitry will affect placement and timing, no guarantee can be given that these figures will be repeatable in a larger design.

Versal ACAP

Part Information			Configuration Parameters												Performance and Resource Utilization
Device	Package	Speed Grade	Configuration Name	AXI_ID_WIDTH	AXI_ADDR_WIDTH	AXI_DATA_WIDTH	AXI_AWUSER_WIDTH	AXI_WUSER_WIDTH	AXI_BUSER_WIDTH	AXI_ARUSER_WIDTH	AXI_RUSER_WIDTH	OUTSTANDING_SUPPORT_RD	ECC_TYPE	EN_ERROR_INJECT	Clock Input	Fmax (MHz)	LUTs	FFs	DSPs	36k BRAMs	18k BRAMs	Speedfile Status
xcvc1902	vsva2197	1LP	soft_ecc_config_0	1	32	8	1	1	1	1	1	1	hamming	true	s_aclk	610	332	464	0	0	0	PRODUCTION 2.11 2022-11-23
xcvc1902	vsva2197	1LP	soft_ecc_config_1	1	32	16	1	1	1	1	1	1	hamming	true	s_aclk	556	385	522	0	0	0	PRODUCTION 2.11 2022-11-23
xcvc1902	vsva2197	1LP	soft_ecc_config_10	1	32	64	1	1	1	1	1	1	HSIAO	true	s_aclk	548	729	859	0	0	0	PRODUCTION 2.11 2022-11-23
xcvc1902	vsva2197	1LP	soft_ecc_config_11	1	32	128	1	1	1	1	1	1	HSIAO	true	s_aclk	508	1051	1320	0	0	0	PRODUCTION 2.11 2022-11-23
xcvc1902	vsva2197	1LP	soft_ecc_config_12	1	32	256	1	1	1	1	1	1	HSIAO	true	s_aclk	423	2001	2206	0	0	0	PRODUCTION 2.11 2022-11-23
xcvc1902	vsva2197	1LP	soft_ecc_config_13	1	32	512	1	1	1	1	1	1	HSIAO	true	s_aclk	469	4261	4218	0	0	0	PRODUCTION 2.11 2022-11-23
xcvc1902	vsva2197	1LP	soft_ecc_config_2	1	32	32	1	1	1	1	1	1	hamming	true	s_aclk	524	522	636	0	0	0	PRODUCTION 2.11 2022-11-23
xcvc1902	vsva2197	1LP	soft_ecc_config_3	1	32	64	1	1	1	1	1	1	hamming	true	s_aclk	485	704	856	0	0	0	PRODUCTION 2.11 2022-11-23
xcvc1902	vsva2197	1LP	soft_ecc_config_4	1	32	128	1	1	1	1	1	1	hamming	true	s_aclk	477	1164	1305	0	0	0	PRODUCTION 2.11 2022-11-23
xcvc1902	vsva2197	1LP	soft_ecc_config_5	1	32	256	1	1	1	1	1	1	hamming	true	s_aclk	415	2110	2207	0	0	0	PRODUCTION 2.11 2022-11-23
xcvc1902	vsva2197	1LP	soft_ecc_config_6	1	32	512	1	1	1	1	1	1	hamming	true	s_aclk	469	4259	4133	0	0	0	PRODUCTION 2.11 2022-11-23
xcvc1902	vsva2197	1LP	soft_ecc_config_7	1	32	8	1	1	1	1	1	1	HSIAO	true	s_aclk	610	334	467	0	0	0	PRODUCTION 2.11 2022-11-23
xcvc1902	vsva2197	1LP	soft_ecc_config_8	1	32	16	1	1	1	1	1	1	HSIAO	true	s_aclk	594	388	520	0	0	0	PRODUCTION 2.11 2022-11-23
xcvc1902	vsva2197	1LP	soft_ecc_config_9	1	32	32	1	1	1	1	1	1	HSIAO	true	s_aclk	579	555	631	0	0	0	PRODUCTION 2.11 2022-11-23

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