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ChipScope Pro Debugging Strategies
Use the following strategies when using the ChipScope™ Pro software for design debugging. For detailed information on how to implement these strategies, see the ChipScope Documentation.
Timing Constraints
When working with timing constraints in the ChipScope Pro cores, be sure to do the following:
  •  If you move the ChipScope Pro NGC netlists, you must also move the associated NCF files.
    When ChipScope Pro cores are created, a netlist constraints file (NCF) is created for each core along with the NGC file. The NCF files contain timing constraints to control the clocks within the ChipScope Pro cores. If you move the NGC netlists to a different directory, you must also move the corresponding NCF files.
  •  Try using a guided design.
    High speed designs may benefit from the use of a guided design. After your design meets all of your requirements, instrument the design using the ChipScope Pro Core Inserter to maintain the existing post-synthesis signal names. Then, run design implementation using a guided flow. This preserves your placing and routing when instantiating ChipScope Pro cores. For more information on guiding your design, see Using SmartGuide.
Core Modification
After inserting the ChipScope Pro ILA cores, whether through black box instantiation of cores created with the Xilinx® CORE Generator or through direct netlist insertion using the ChipScope Pro Core Inserter, you must implement your design. After running the Place and Route process, you can modify data or trigger signals in the cores using FPGA Editor. Open your routed design in FPGA Editor, and select the Tools > ILA command to open the ILA dialog box. You can then click the Change Net option to reroute internal signals without having to modify your HDL file or ChipScope Core Inserter options. For information, see Using the ILA Command in the FPGA Editor Help.
Note Not all signal connections may be visible in FPGA Editor, because ChipScope Pro logic may have been optimized into the logic of the design.
Signal Annotation
When you first load a design in the ChipScope Pro Analyzer, the names for the data signals are generic, because the set of logical connections in the FPGA is the only information available to the software. You must set the names of the signals connected to the trigger and data ports. You can set the names in the following ways:
  •  If you used the ChipScope Pro Core Inserter or the Synplicity Certify® software to insert the cores, you can use the ChipScope Pro Analyzer to modify the signal names.
    In Project Navigator, double-click Analyze Design Using Chipscope to launch the ChipScope Pro Analyzer. Use the File > Import command to import the CDC file, and rename your signal, bus, or trigger port using the Rename command. For details, see the "Importing Signal Names" section in the "Using the ChipScope Pro Analyzer" chapter of the ChipScope Pro Software and Cores User Manual available from the ChipScope Documentation.
  •  If you used the Xilinx CORE Generator to create the cores and instantiated the cores in your HDL file, you can use either of the following methods to annotate the signals:
    •  Open your routed design in the FPGA Editor, and use the Tools > ILA command to open the ILA dialog box. You can then click the Write CDC option to create a new CDC file that contains all the signal connection information available the FPGA Editor. For information, see Using the ILA Command in the FPGA Editor Help.
    •  In the ChipScope Pro Analyzer, right-click the signal and select Rename. You can create buses and store all of your modifications in the ChipScope Pro Analyzer project.
Token Files
You can use the ChipScope Pro Analyzer waveform or listing viewers to tokenize bus values. Tokens are string labels that are defined in a separate ASCII file and can be assigned to a particular bus value. These labels can be useful in applications such as address decoding and state machines.
To show values as text, you must first create a token (TOK) file. Then, enter tokens in the TOK file using the following syntax:
NAME=VALUE
where NAME is the token name and VALUE is the token value.
By default, token values are read as hexadecimal, but you can specify binary or decimal format in the TOK file if you prefer. When you create a bus in the ChipScope Pro Analyzer, you can right-click the bus and select Radix > Token, and specify the TOK file you created.
Note You can see a sample token file in the token subdirectory of the directory where ChipScope Pro was installed.
User Logic
In addition to using ChipScope Pro cores to debug, you can add user logic to the cores to improve the efficiency of the debugging process. For example, you can use VIO core outputs to introduce a control signal that  multiplexes data or triggers buses that connect to an ILA core. Adding a minimum of user logic can provide access to multiple portions of your design using just one ILA core and no design recompilation. You can also add user logic to VIO core inputs to create a glitch detection interface. Any activity on a signal is then reported in the ChipScope Pro Analyzer VIO Console. For more information, see the ChipScope Pro Software and Cores User Manual available from the ChipScope Documentation.
See Also

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