Debugging Strategies using FPGA Editor
FPGA Editor allows you to view and verify the post-Place and Route implementation of your design at a detailed level. You can use it to check placement, routing, and programming of design components as well as check timing on signals and paths. FPGA Editor allows you to directly modify the physical design, so you can quickly make simple programming changes, such as signal inversion, or routing changes without having to re-implement your design. You can use the following strategies when quick programming changes are needed, such as in a lab environment.
Note To launch FPGA Editor, expand the Place & Route process in the Project Navigator Processes tab, and double-click View/Edit Routed Design (FPGA Editor). For detailed information on using FPGA Editor, see the FPGA Editor Help.
Use the FPGA Editor Tools > Probes command to perform real-time debugging when you want to analyze a few signals at a time. Using the Probes command, you can identify and route internal signals to available I/O pins without rerunning the place and route tools. You can then monitor the real-time signal activity using normal lab test equipment, such as logic and state analyzers or oscilloscopes. For more information, see Using Probes.
Route Delays
You can use the FPGA Editor Tools > Delay command or the corresponding Delay button to find the delays for a selected signal as follows:
  •  Delay of a signal from its driver to all loads
    Select a signal for which you need delay characteristics, and click Delay. The List window shows the delay value from the driver to each load.
  •  Delay for a source-destination pair
    Select the driver and load pins for a signal, and click Delay. The List window shows the delay value of the routing for the selected driver and load.
For more information, see Verifying Your Design.
Verification of Clock Resource Placement
You can minimize clock delay and skew by containing all loads within the device clock regions. In FPGA Editor, you can view the routing for each clock by selecting the global clock signals using any of the following methods:
  •  In the Array window, click the signal to select it.
  •  In the List window, click the signal to display it in the Array window.
  •  Select Edit > Find to find the signals in the Array window.
You can then verify the placement for all the clock loads are contained within the clock region boundaries. For more information, see Selecting Objects.
Note For details about the clock region in the device you are using, see the Data Sheet for your device.
Cross Probing from the Timing Analyzer
You can cross probe from a timing report in Timing Analyzer to FPGA Editor. From FPGA Editor, select Tools > Timing Report. From the timing report in Timing Analyzer, you can select individual nets or entire paths to highlight the corresponding nets or paths in the FPGA Editor Array window.
See Also

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